print spec control MSRs

Change-Id: I093f94bfd26e517ca124b6af051fa8e0045030f2

cpucounters.cpp

@@ -1746,6 +1746,8 @@ PCM::PCM() :
 
     if(!detectNominalFrequency()) return;
 
+    showSpecControlMSRs();
+
 #ifdef __linux__
     if (isNMIWatchdogEnabled())
     {
@@ -1799,6 +1801,30 @@ void PCM::enableJKTWorkaround(bool enable)
     }
 }
 
+void PCM::showSpecControlMSRs()
+{
+    PCM_CPUID_INFO cpuinfo;
+    pcm_cpuid(7, 0, cpuinfo);
+
+    if (MSR.size())
+    {
+        if ((cpuinfo.reg.edx & (1 << 26)) || (cpuinfo.reg.edx & (1 << 27)))
+        {
+            uint64 val64 = 0;
+            MSR[0]->read(MSR_IA32_SPEC_CTRL, &val64);
+            std::cout << "IBRS enabled in the kernel   : " << ((val64 & 1) ? "yes" : "no") << std::endl;
+            std::cout << "STIBP enabled in the kernel  : " << ((val64 & 2) ? "yes" : "no") << std::endl;
+        }
+        if (cpuinfo.reg.edx & (1 << 29))
+        {
+            uint64 val64 = 0;
+            MSR[0]->read(MSR_IA32_ARCH_CAPABILITIES, &val64);
+            std::cout << "The processor is not susceptible to Rogue Data Cache Load: " << ((val64 & 1) ? "yes" : "no") << std::endl;
+            std::cout << "The processor supports enhanced IBRS                     : " << ((val64 & 2) ? "yes" : "no") << std::endl;
+        }
+    }
+}
+
 bool PCM::isCoreOnline(int32 os_core_id) const
 {
     return (topology[os_core_id].os_id != -1) && (topology[os_core_id].core_id != -1) && (topology[os_core_id].socket != -1);

cpucounters.h

@@ -782,6 +782,7 @@ class PCM_API PCM
     void printSystemTopology() const;
     bool initMSR();
     bool detectNominalFrequency();
+    void showSpecControlMSRs();
     void initEnergyMonitoring();
     void initUncoreObjects();
     /*!

types.h

@@ -930,6 +930,9 @@ struct IIOPMUCNTCTLRegister
 
 #define MSR_PERF_GLOBAL_INUSE   (0x392)
 
+#define MSR_IA32_SPEC_CTRL         (0x48)
+#define MSR_IA32_ARCH_CAPABILITIES (0x10A)
+
 #ifdef _MSC_VER
 #include <windows.h>
 // data structure for converting two uint32s <-> uin64