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Truncate all ALU32 except for bit-endianess
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Signed-off-by: Alan Jowett <[email protected]>
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Alan-Jowett committed May 18, 2024
1 parent 5a4f6c6 commit 5f4c21a
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Showing 3 changed files with 11 additions and 3 deletions.
6 changes: 6 additions & 0 deletions vm/ubpf_jit_x86_64.c
Original file line number Diff line number Diff line change
Expand Up @@ -769,6 +769,12 @@ translate(struct ubpf_vm* vm, struct jit_state* state, char** errmsg)
state->jit_status = UnknownInstruction;
*errmsg = ubpf_error("Unknown instruction at PC %d: opcode %02x", i, inst.opcode);
}

// If this is a ALU32 instruction, truncate the target register to 32 bits.
if (((inst.opcode & EBPF_CLS_MASK) == EBPF_CLS_ALU) &&
(inst.opcode & EBPF_ALU_OP_MASK) != 0xd0) {
emit_truncate_u32(state, dst);
}
}

if (state->jit_status != NoError) {
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6 changes: 4 additions & 2 deletions vm/ubpf_vm.c
Original file line number Diff line number Diff line change
Expand Up @@ -737,7 +737,7 @@ ubpf_exec_ex(
}
break;
case EBPF_OP_JEQ32_REG:
if (u32(reg[inst.dst]) == reg[inst.src]) {
if (u32(reg[inst.dst]) == u32(reg[inst.src])) {
pc += inst.offset;
}
break;
Expand Down Expand Up @@ -1003,6 +1003,9 @@ ubpf_exec_ex(
// valid.
break;
}
if (((inst.opcode & EBPF_CLS_MASK) == EBPF_CLS_ALU) && (inst.opcode & EBPF_ALU_OP_MASK) != 0xd0) {
reg[inst.dst] &= UINT32_MAX;
}
}

cleanup:
Expand Down Expand Up @@ -1371,7 +1374,6 @@ ubpf_get_registers(const struct ubpf_vm* vm)
fprintf(stderr, "uBPF warning: registers are not exposed in release mode. Please recompile in debug mode\n");
return NULL;
}

#endif

typedef struct _ebpf_encoded_inst
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