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Merge tag 'LA.UM.9.12.r1-14300-SMxx50.0' of https://git.codelinaro.or…
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"LA.UM.9.12.r1-14300-SMxx50.0"

* tag 'LA.UM.9.12.r1-14300-SMxx50.0' of https://git.codelinaro.org/clo/la/platform/vendor/qcom-opensource/wlan/fw-api: (23 commits)
  fw-api: CL 18227240 - update fw common interface files
  fw-api: CL 18225673 - update fw common interface files
  fw-api: CL 18211442 - update fw common interface files
  fw-api: CL 18197955 - update fw common interface files
  fw-api: CL 18177396 - update fw common interface files
  fw-api: CL 18177389 - update fw common interface files
  fw-api: CL 18173549 - update fw common interface files
  fw-api: add rx_reo_queue_1k.h file for 1K BA window support
  fw-api: CL 18137973 - update fw common interface files
  fw-api: CL 18119950 - update fw common interface files
  fw-api: CL 18116081 - update fw common interface files
  fw-api: CL 18116079 - update fw common interface files
  fw-api: CL 18101507 - update fw common interface files
  fw-api: CL 18098896 - update fw common interface files
  fw-api: CL 18096193 - update fw common interface files
  fw-api: CL 18082017 - update fw common interface files
  fw-api: CL 18082015 - update fw common interface files
  fw-api: CL 18037073 - update fw common interface files
  fw-api: CL 18037070 - update fw common interface files
  fw-api: CL 18000081 - update fw common interface files
  ...

Signed-off-by: Carlos Jimenez (JavaShin-X) <[email protected]>
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javashin committed Jun 16, 2022
2 parents 9be9b52 + c646975 commit 9813484
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526 changes: 523 additions & 3 deletions drivers/staging/fw-api/fw/htt.h
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116 changes: 116 additions & 0 deletions drivers/staging/fw-api/fw/htt_ppdu_stats.h
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Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2017-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
Expand Down Expand Up @@ -53,6 +54,8 @@ enum htt_ppdu_stats_tlv_tag {
HTT_PPDU_STATS_USR_COMPLTN_BA_BITMAP_1024_TLV,/* htt_ppdu_stats_user_compltn_ba_bitmap_1024_tlv */
HTT_PPDU_STATS_RX_MGMTCTRL_PAYLOAD_TLV, /* htt_ppdu_stats_rx_mgmtctrl_payload_tlv */
HTT_PPDU_STATS_FOR_SMU_TLV, /* htt_ppdu_stats_for_smu_tlv */
HTT_PPDU_STATS_MLO_TX_RESP_TLV, /* htt_ppdu_stats_mlo_tx_resp_tlv */
HTT_PPDU_STATS_MLO_TX_NOTIFICATION_TLV, /* htt_ppdu_stats_mlo_tx_notification_tlv */

/* New TLV's are added above to this line */
HTT_PPDU_STATS_MAX_TAG,
Expand Down Expand Up @@ -2844,4 +2847,117 @@ typedef struct {
A_UINT32 ba_bitmap[1];
} htt_ppdu_stats_for_smu_tlv;

typedef struct {
htt_tlv_hdr_t tlv_hdr;
/*
* BIT [ 2 : 0] :- response_reason
* BIT [ 6 : 3] :- mlo_change_t1_cts2self
* BIT [ 10 : 7] :- mlo_change_t1_ppdu
* BIT [ 14 : 11] :- mlo_change_t2_response
* BIT [ 18 : 15] :- mlo_change_t3_r2r
* BIT [ 19 : 19] :- partner_link_info_valid
* BIT [ 22 : 20] :- partner_link_id
* BIT [ 27 : 23] :- partner_link_cmd_ring_id
* BIT [ 28 : 28] :- dot11ax_trigger_frame_embedded
* BIT [ 31 : 29] :- reserved_0a
*/
A_UINT32 response_reason : 3,
mlo_change_t1_cts2self : 4,
mlo_change_t1_ppdu : 4,
mlo_change_t2_response : 4,
mlo_change_t3_r2r : 4,
partner_link_info_valid : 1,
partner_link_id : 3,
partner_link_cmd_ring_id : 5,
dot11ax_trigger_frame_embedded : 1,
reserved_0a : 3;
/*
* BIT [ 15 : 0] :- partner_link_schedule_id
* BIT [ 31 : 16] :- tx_rx_overlap_duration (microsecond units)
*/
A_UINT32 partner_link_schedule_id : 16,
tx_rx_overlap_duration_us : 16;
/*
* BIT [ 15 : 0] :- cts2self_duration (microsecond units)
* BIT [ 31 : 16] :- ppdu_duration (microsecond units)
*/
A_UINT32 cts2self_duration_us : 16,
ppdu_duration_us : 16;
/*
* BIT [ 15 : 0] :- response_duration (microsecond units)
* BIT [ 31 : 16] :- response_to_response_duration (microsecond units)
*/
A_UINT32 response_duration_us : 16,
response_to_response_duration_us : 16;
/*
* BIT [ 15 : 0] :- self_link_schedule_id
* BIT [ 31 : 16] :- hls_branch_debug_code
*/
A_UINT32 self_link_schedule_id : 16,
hls_branch_debug_code : 16;
/*
* BIT [ 31 : 0] :- hls_decision_debug_info
*/
A_UINT32 hls_decision_debug_info : 32;
} htt_ppdu_stats_mlo_tx_resp_tlv;

typedef struct {
htt_tlv_hdr_t tlv_hdr;
/*
* BIT [ 2 : 0] :- notification_reason
* BIT [ 3 : 3] :- ml_decision
* BIT [ 4 : 4] :- cts2self_padding
* BIT [ 5 : 5] :- initiated_by_truncated_backoff
* BIT [ 8 : 6] :- transmit_start_reason
* BIT [ 14 : 9] :- num_users
* BIT [ 24 : 15] :- nstr_mlo_sta_id
* BIT [ 25 : 25] :- block_self_ml_sync
* BIT [ 26 : 26] :- block_partner_ml_sync
* BIT [ 27 : 27] :- nstr_mlo_sta_id_valid
* BIT [ 31 : 28] :- reserved_0a
*/
A_UINT32 notification_reason : 3,
ml_decision : 1,
cts2self_padding : 1,
initiated_by_truncated_backoff : 1,
transmit_start_reason : 3,
num_users : 6,
nstr_mlo_sta_id : 10,
block_self_ml_sync : 1,
block_partner_ml_sync : 1,
nstr_mlo_sta_id_valid : 1,
reserved_0a : 4;
/*
* BIT [ 15 : 0] :- pdg_ppdu_duration_adjust_value (microsecond units)
* BIT [ 31 : 16] :- mlo_ppdu_duration_adjust_value (microsecond units)
*/
A_UINT32 pdg_ppdu_duration_adjust_value_us : 16,
mlo_ppdu_duration_adjust_value_us : 16;
/*
* BIT [ 15 : 0] :- response_duration (microsecond units)
* BIT [ 31 : 16] :- response_to_response_duration (microsecond units)
*/
A_UINT32 response_duration_us : 16,
response_to_response_duration_us : 16;
/*
* BIT [ 15 : 0] :- schedule_id
* BIT [ 20 : 16] :- cmd_ring_id
* BIT [ 31 : 21] :- reserved_1a
*/
A_UINT32 schedule_id : 16,
cmd_ring_id : 5,
reserved_1a : 11;
/*
* BIT [ 31 : 0] :- mlo_reference_timestamp (microsecond units)
*/
A_UINT32 mlo_reference_timestamp_us : 32;
/*
* BIT [ 15 : 0] :- cts2self_duration (microsecond units)
* BIT [ 31 : 16] :- ppdu_duration (microsecond units)
*/
A_UINT32 cts2self_duration_us : 16,
ppdu_duration_us : 16;
} htt_ppdu_stats_mlo_tx_notification_tlv;


#endif //__HTT_PPDU_STATS_H__
155 changes: 155 additions & 0 deletions drivers/staging/fw-api/fw/htt_stats.h
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Original file line number Diff line number Diff line change
Expand Up @@ -4653,6 +4653,8 @@ typedef struct {
A_UINT32 ax_su_embedded_trigger_data_ppdu;
/** 11AX HE SU data + embedded trigger PPDU failure stats (stats for HETP ack failure PPDU cnt) */
A_UINT32 ax_su_embedded_trigger_data_ppdu_err;
/** sta side trigger stats */
A_UINT32 trigger_type_11be[HTT_TX_PDEV_STATS_NUM_11BE_TRIGGER_TYPES];
} htt_tx_pdev_rate_stats_tlv;

typedef struct {
Expand Down Expand Up @@ -5210,6 +5212,22 @@ typedef struct {
A_UINT32 rx_ulofdma_data_nusers;
} htt_rx_pdev_ul_ofdma_user_stats_tlv;

typedef struct {
htt_tlv_hdr_t tlv_hdr;

A_UINT32 user_index;
/** PPDU level */
A_UINT32 be_rx_ulofdma_non_data_ppdu;
/** PPDU level */
A_UINT32 be_rx_ulofdma_data_ppdu;
/** MPDU level */
A_UINT32 be_rx_ulofdma_mpdu_ok;
/** MPDU level */
A_UINT32 be_rx_ulofdma_mpdu_fail;
A_UINT32 be_rx_ulofdma_non_data_nusers;
A_UINT32 be_rx_ulofdma_data_nusers;
} htt_rx_pdev_be_ul_ofdma_user_stats_tlv;

typedef struct {
htt_tlv_hdr_t tlv_hdr;

Expand Down Expand Up @@ -5333,6 +5351,8 @@ typedef struct {
A_INT8 be_rx_ul_mumimo_fd_rssi[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS];
/** Average pilot EVM measued for RX UL TB PPDU */
A_INT8 be_rx_ulmumimo_pilot_evm_dB_mean[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS];
/** Number of times UL MUMIMO TB PPDUs received in a punctured mode */
A_UINT32 rx_ul_mumimo_punctured_mode[HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS];
} htt_rx_pdev_ul_mumimo_trig_be_stats_tlv;

/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS
Expand Down Expand Up @@ -6039,15 +6059,25 @@ typedef struct {
A_UINT32 sounding[HTT_TX_NUM_OF_SOUNDING_STATS_WORDS];

/* cv upload handler stats */
/** total times CV nc mismatched */
A_UINT32 cv_nc_mismatch_err;
/** total times CV has FCS error */
A_UINT32 cv_fcs_err;
/** total times CV has invalid NSS index */
A_UINT32 cv_frag_idx_mismatch;
/** total times CV has invalid SW peer ID */
A_UINT32 cv_invalid_peer_id;
/** total times CV rejected because TXBF is not setup in peer */
A_UINT32 cv_no_txbf_setup;
/** total times CV expired while in updating state */
A_UINT32 cv_expiry_in_update;
/** total times Pkt b/w exceeding the cbf_bw */
A_UINT32 cv_pkt_bw_exceed;
/** total times CV DMA not completed */
A_UINT32 cv_dma_not_done_err;
/** total times CV update to peer failed */
A_UINT32 cv_update_failed;

/* cv query stats */
/** total times CV query happened */
A_UINT32 cv_total_query;
Expand Down Expand Up @@ -6092,6 +6122,16 @@ typedef struct {
A_UINT32 cv_found_upload_in_progress;
/** Expired CV found during query. */
A_UINT32 cv_expired_during_query;
/** total times CV dma timeout happened */
A_UINT32 cv_dma_timeout_error;
/** total times CV bufs uploaded for IBF case */
A_UINT32 cv_buf_ibf_uploads;
/** total times CV bufs uploaded for EBF case */
A_UINT32 cv_buf_ebf_uploads;
/** total times CV bufs received from IPC ring */
A_UINT32 cv_buf_received;
/** total times CV bufs fed back to the IPC ring */
A_UINT32 cv_buf_fed_back;
} htt_tx_sounding_stats_tlv;

/* STATS_TYPE : HTT_DBG_EXT_STATS_TX_SOUNDING_INFO
Expand Down Expand Up @@ -6529,6 +6569,7 @@ typedef struct {
typedef enum {
HTT_STATS_RC_MODE_DLSU = 0,
HTT_STATS_RC_MODE_DLMUMIMO = 1,
HTT_STATS_RC_MODE_DLOFDMA = 2,
} htt_stats_rc_mode;

typedef struct {
Expand All @@ -6551,6 +6592,12 @@ typedef enum {
HTT_RC_MODE_2D_COUNT,
} HTT_RC_MODE;

typedef enum {
HTT_STATS_RU_TYPE_INVALID = 0,
HTT_STATS_RU_TYPE_SINGLE_RU_ONLY = 1,
HTT_STATS_RU_TYPE_SINGLE_AND_MULTI_RU = 2,
} htt_stats_ru_type;

typedef struct {
htt_tlv_hdr_t tlv_hdr;

Expand All @@ -6573,6 +6620,9 @@ typedef struct {
htt_tx_rate_stats_t per_bw320;

A_UINT32 probe_cnt_per_rcmode[HTT_RC_MODE_2D_COUNT];

htt_stats_ru_type ru_type; /* refer to htt_stats_ru_type */
htt_tx_rate_stats_t per_ru[HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS];
} htt_tx_rate_stats_per_tlv;

/* NOTE:
Expand Down Expand Up @@ -6993,6 +7043,36 @@ typedef enum {
HTT_STATS_NO_RESET_SCAN_BACK_TO_SAME_HOME_CHANNEL_CHANGE = 0x00800000, /* No reset, scan to home channel change */
} HTT_STATS_RESET_CAUSE;

typedef enum {
HTT_CHANNEL_RATE_FULL,
HTT_CHANNEL_RATE_HALF,
HTT_CHANNEL_RATE_QUARTER,

HTT_CHANNEL_RATE_COUNT
} HTT_CHANNEL_RATE;

typedef enum {
HTT_PHY_BW_IDX_20MHz = 0,
HTT_PHY_BW_IDX_40MHz = 1,
HTT_PHY_BW_IDX_80MHz = 2,
HTT_PHY_BW_IDX_80Plus80 = 3,
HTT_PHY_BW_IDX_160MHz = 4,
HTT_PHY_BW_IDX_10MHz = 5,
HTT_PHY_BW_IDX_5MHz = 6,
HTT_PHY_BW_IDX_165MHz = 7,

} HTT_PHY_BW_IDX;

typedef enum {
HTT_WHAL_CONFIG_NONE = 0x00000000,
HTT_WHAL_CONFIG_NF_WAR = 0x00000001,
HTT_WHAL_CONFIG_CAL_WAR = 0x00000002,
HTT_WHAL_CONFIG_DO_NF_CAL = 0x00000004,
HTT_WHAL_CONFIG_SET_WAIT_FOR_NF_CAL = 0x00000008,
HTT_WHAL_CONFIG_FORCED_TX_PWR = 0x00000010,
HTT_WHAL_CONFIG_FORCED_GAIN_IDX = 0x00000020,
HTT_WHAL_CONFIG_FORCED_PER_CHAIN = 0x00000040,
} HTT_WHAL_CONFIG;

typedef struct {
htt_tlv_hdr_t tlv_hdr;
Expand Down Expand Up @@ -7149,6 +7229,34 @@ typedef struct {
*/
A_UINT32 rxdesense_thresh_sw;
A_UINT32 rxdesense_thresh_hw;
/** Current PHY Bandwidth -
* values are specified by the HTT_PHY_BW_IDX enum type
*/
A_UINT32 phy_bw_code;
/** Current channel operating rate -
* values are specified by the HTT_CHANNEL_RATE enum type
*/
A_UINT32 phy_rate_mode;
/** current channel operating band
* 0 - 5G; 1 - 2G; 2 -6G
*/
A_UINT32 phy_band_code;
/** microcode processor virtual phy base address -
* provided only for debug
*/
A_UINT32 phy_vreg_base;
/** microcode processor virtual phy base ext address -
* provided only for debug
*/
A_UINT32 phy_vreg_base_ext;
/** HW LUT table configuration for home/scan channel -
* provided only for debug
*/
A_UINT32 cur_table_index;
/** SW configuration flag for PHY reset and Calibrations -
* values are specified by the HTT_WHAL_CONFIG enum type
*/
A_UINT32 whal_config_flag;
} htt_phy_reset_stats_tlv;

typedef struct {
Expand All @@ -7168,8 +7276,54 @@ typedef struct {

/** phyoff count during rfmode switch */
A_UINT32 rf_mode_switch_phy_off_cnt;

/** Temperature based recalibration count */
A_UINT32 temperature_recal_cnt;
} htt_phy_reset_counters_tlv;

/* Considering 320 MHz maximum 16 power levels */
#define HTT_MAX_CH_PWR_INFO_SIZE 16

typedef struct {
htt_tlv_hdr_t tlv_hdr;

/** current pdev_id */
A_UINT32 pdev_id;

/** Tranmsit power control scaling related configurations */
A_UINT32 tx_power_scale;
A_UINT32 tx_power_scale_db;

/** Minimum negative tx power supported by the target */
A_INT32 min_negative_tx_power;

/** current configured CTL domain */
A_UINT32 reg_ctl_domain;

/** Regulatory power information for the current channel */
A_INT32 max_reg_allowed_power[HTT_STATS_MAX_CHAINS];
A_INT32 max_reg_allowed_power_6g[HTT_STATS_MAX_CHAINS];
/** channel max regulatory power in 0.5dB */
A_UINT32 twice_max_rd_power;

/** current channel and home channel's maximum possible tx power */
A_INT32 max_tx_power;
A_INT32 home_max_tx_power;

/** channel's Power Spectral Density */
A_UINT32 psd_power;
/** channel's EIRP power */
A_UINT32 eirp_power;
/** 6G channel power mode
* 0-LPI, 1-SP, 2-VLPI and 3-SP_CLIENT power mode
*/
A_UINT32 power_type_6ghz;

/** sub-band channels and corresponding Tx-power */
A_UINT32 sub_band_cfreq[HTT_MAX_CH_PWR_INFO_SIZE];
A_UINT32 sub_band_txpower[HTT_MAX_CH_PWR_INFO_SIZE];
} htt_phy_tpc_stats_tlv;

/* NOTE:
* This structure is for documentation, and cannot be safely used directly.
* Instead, use the constituent TLV structures to fill/parse.
Expand All @@ -7179,6 +7333,7 @@ typedef struct {
htt_phy_stats_tlv phy_stats;
htt_phy_reset_counters_tlv phy_reset_counters;
htt_phy_reset_stats_tlv phy_reset_stats;
htt_phy_tpc_stats_tlv phy_tpc_stats;
} htt_phy_counters_and_phy_stats_t;

/* NOTE:
Expand Down
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