Issue#1061: Updates for pragma use cases (#1063)

* Issue#1061:  Updates for pragma use cases

Pragmas are now treated as comments:

  *  Pragmas are now a subclass of comments
  *  Move rules will not move tokens if it crosses a pragma

* Fixing issue with expression classification causing infinite loop.

docs/block_rules.rst

@@ -65,7 +65,7 @@ This rule checks the **is** keyword is on the same line as the **block** keyword
 
 .. code-block:: vhdl
 
-   block_labeel : block is
+   block_label : block is
 
 block_004
 #########

vsg/__parser__.py

@@ -47,7 +47,7 @@ def main():
 
     configuration = config.New(commandLineArguments)
 
-    oVhdlFile = vhdlFile.vhdlFile(lLines[0], None, None, configuration)
+    oVhdlFile = vhdlFile.vhdlFile(lLines[0], commandLineArguments, None, None, configuration)
     oVhdlFile.filename = sFileName
 
     utils.print_objects(oVhdlFile, not commandLineArguments.whitespace)

vsg/rules/block/rule_003.py

@@ -28,7 +28,7 @@ class rule_003(move_token_to_the_right_of_several_possible_tokens_if_it_exists_b
 
     .. code-block:: vhdl
 
-       block_labeel : block is
+       block_label : block is
     '''
 
     def __init__(self):

vsg/rules/move_token.py

@@ -38,11 +38,13 @@ def __init__(self, name, identifier, oToken):
 
     def _get_tokens_of_interest(self, oFile):
         if self.action == 'new_line' and not self.preserve_comment:
-            return get_toi_for_new_line_option(self, oFile)
+            lToi = get_toi_for_new_line_option(self, oFile)
         elif self.action == 'new_line' and self.preserve_comment:
-            return get_toi_for_new_line_option_with_preserve_comment(self, oFile)
+            lToi = get_toi_for_new_line_option_with_preserve_comment(self, oFile)
         else:
-            return get_toi_for_move_left_option(self, oFile)
+            lToi = get_toi_for_move_left_option(self, oFile)
+
+        return rules_utils.remove_tois_with_pragmas(lToi)
 
     def _analyze(self, lToi):
         if self.action == 'new_line' and not self.preserve_comment:

vsg/rules/move_token_left_to_next_non_whitespace_token.py

@@ -1,6 +1,7 @@
 
 
 from vsg import parser
+from vsg import token
 from vsg import violation
 
 from vsg.rules import utils as rules_utils
@@ -46,6 +47,8 @@ def _get_tokens_of_interest(self, oFile):
             lTokens = oToi.get_tokens()
             if skip_based_on_whitespace(self.bInsertWhitespace, lTokens):
                 continue
+            if oToi.token_type_exists(token.pragma.pragma):
+                continue
             lReturn.append(oToi)
         return lReturn
 

vsg/rules/move_token_next_to_another_token.py

@@ -36,7 +36,8 @@ def __init__(self, name, identifier, anchor_token, token_to_move):
         self.configuration_documentation_link = None
 
     def _get_tokens_of_interest(self, oFile):
-        return oFile.get_tokens_bounded_by(self.anchor_token, self.token_to_move, bIncludeTillEndOfLine=True)
+        lToi = oFile.get_tokens_bounded_by(self.anchor_token, self.token_to_move, bIncludeTillEndOfLine=True)
+        return rules_utils.remove_tois_with_pragmas(lToi)
 
     def _analyze(self, lToi):
         for oToi in lToi:

vsg/rules/move_token_right_to_next_non_whitespace_token.py

@@ -84,7 +84,7 @@ def filter_toi(self, lToi):
         if skip_based_on_whitespace(self.bInsertWhitespace, oToi):
             continue
         lReturn.append(oToi)
-    return lReturn
+    return rules_utils.remove_tois_with_pragmas(lReturn)
 
 
 def skip_based_on_whitespace(bInsertWhitespace, oToi):

vsg/rules/move_token_sequences_left_of_token.py

@@ -38,7 +38,7 @@ def _get_tokens_of_interest(self, oFile):
                 aToi = oFile.get_tokens_bounded_by(lSequence[0], self.oLeftToken, bIncludeTillBeginningOfLine=True)
                 lToi = utils.combine_two_token_class_lists(lToi, aToi)
             lPrevious.append(lSequence[0])
-        return lToi
+        return rules_utils.remove_tois_with_pragmas(lToi)
 
     def _analyze(self, lToi):
         for oToi in lToi:

vsg/rules/move_token_to_the_right_of_several_possible_tokens_if_it_exists_between_tokens.py

@@ -38,7 +38,8 @@ def __init__(self, name, identifier, oMoveToken, lAnchorTokens, oStartToken, oEn
         self.configuration_documentation_link = None
 
     def _get_tokens_of_interest(self, oFile):
-        return oFile.get_tokens_bounded_by(self.oStartToken, self.oEndToken, bIncludeTillEndOfLine=True)
+        lToi = oFile.get_tokens_bounded_by(self.oStartToken, self.oEndToken, bIncludeTillEndOfLine=True)
+        return rules_utils.remove_tois_with_pragmas(lToi)
 
     def _analyze(self, lToi):
         for oToi in lToi:

vsg/rules/utils.py

@@ -489,3 +489,11 @@ def close_paren_detected_at_end_of_tokens(lTokens):
         return True
     lTokens.reverse()
     return False
+
+
+def remove_tois_with_pragmas(lToi):
+    lReturn = []
+    for oToi in lToi:
+        if not oToi.token_type_exists(token.pragma.pragma):
+            lReturn.append(oToi)
+    return lReturn

vsg/tests/block/rule_001_test_input.fixed.vhd

@@ -8,4 +8,8 @@ begin
 
   BLOCK_LABEL : block is begin end block;
 
+  BLOCK_LABEL :
+  -- synthesis translate_off
+  block is begin end block;
+
 end architecture RTL;

vsg/tests/block/rule_001_test_input.vhd

@@ -8,4 +8,8 @@ begin
   BLOCK_LABEL :
   block is begin end block;
 
+  BLOCK_LABEL :
+  -- synthesis translate_off
+  block is begin end block;
+
 end architecture RTL;

vsg/tests/block/rule_003_test_input.fixed.vhd

@@ -15,4 +15,8 @@ begin
   BLOCK_LABEL : block (guard_condition) is
   begin end block;
 
+  BLOCK_LABEL : block
+  -- synthesis translate_off
+  is begin end block;
+
 end architecture RTL;

vsg/tests/block/rule_003_test_input.vhd

@@ -15,4 +15,8 @@ begin
   BLOCK_LABEL : block (guard_condition)
   is begin end block;
 
+  BLOCK_LABEL : block
+  -- synthesis translate_off
+  is begin end block;
+
 end architecture RTL;

vsg/tests/if_statement/rule_036_test_input.fixed.vhd

@@ -28,6 +28,11 @@ begin
       b <= '1';
     end if;
 
+    if a = '1'
+    -- synthesis translate_off
+    then
+    end if;
+
   end process;
 
 end architecture RTL;

vsg/tests/if_statement/rule_036_test_input.vhd

@@ -33,6 +33,11 @@ begin
       b <= '1';
     end if;
 
+    if a = '1'
+    -- synthesis translate_off
+    then
+    end if;
+
   end process;
 
 end architecture RTL;

vsg/tests/library/rule_007_test_input.fixed_no_blank_line.vhd

@@ -80,3 +80,21 @@ use work.utility_pkg.all;
 package body fifo_pkg is end package body;
 use work.utility_pkg.all;
 
+
+library ieee;
+
+  -- comment
+  use ieee.std_logic_1164.all;
+
+library ieee;
+-- comment
+  use ieee.std_logic_1164.all;
+
+library ieee;
+  use ieee.std_logic_1164.all;
+
+-- comment
+-- comment
+-- comment
+  use work.all;
+

vsg/tests/library/rule_007_test_input.fixed_no_blank_line_unless_different_library.vhd

@@ -89,3 +89,21 @@ use work.utility_pkg.all;
 package body fifo_pkg is end package body;
 use work.utility_pkg.all;
 
+
+library ieee;
+
+  -- comment
+  use ieee.std_logic_1164.all;
+
+library ieee;
+-- comment
+  use ieee.std_logic_1164.all;
+
+library ieee;
+  use ieee.std_logic_1164.all;
+
+-- comment
+-- comment
+-- comment
+  use work.all;
+

vsg/tests/library/rule_007_test_input.vhd

@@ -98,3 +98,22 @@ use work.utility_pkg.all;
 package body fifo_pkg is end package body;
 use work.utility_pkg.all;
 
+
+library ieee;
+
+  -- comment
+
+  use ieee.std_logic_1164.all;
+
+library ieee;
+-- comment
+  use ieee.std_logic_1164.all;
+
+library ieee;
+  use ieee.std_logic_1164.all;
+
+-- comment
+-- comment
+-- comment
+  use work.all;
+

vsg/tests/library/test_rule_007.py

@@ -25,7 +25,7 @@ def test_rule_007_no_blank_line(self):
         self.assertEqual(oRule.name, 'library')
         self.assertEqual(oRule.identifier, '007')
 
-        lExpected = [11, 16, 22, 24, 27, 33, 42, 51, 60, 69, 78, 87, 96]
+        lExpected = [11, 16, 22, 24, 27, 33, 42, 51, 60, 69, 78, 87, 96, 106]
 
         oRule.analyze(self.oFile)
         self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
@@ -51,7 +51,7 @@ def test_rule_007_no_blank_line_unless_different_library(self):
         oRule = library.rule_007()
         oRule.style = 'no_blank_line_unless_different_library'
 
-        lExpected = [11, 16, 22, 27]
+        lExpected = [11, 16, 22, 27, 106]
 
         oRule.analyze(self.oFile)
         self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))

vsg/tests/port/rule_014_test_input.fixed.vhd

@@ -17,3 +17,15 @@ entity FIFO is
     O_DATA  : out std_logic_vector(31 downto 0)
 );
 end entity FIFO;
+
+
+entity FIFO is
+  port (
+    I_WR_EN : in  std_logic;
+    I_DATA  : out std_logic_vector(31 downto 0);
+    I_RD_EN : in  std_logic;
+    O_DATA  : out std_logic_vector(31 downto 0)
+  -- synthesis translate_off
+  );
+end entity FIFO;
+

vsg/tests/port/rule_014_test_input.fixed_move_left.vhd

@@ -16,3 +16,15 @@ entity FIFO is
     I_RD_EN : in  std_logic;
     O_DATA  : out std_logic_vector(31 downto 0));
 end entity FIFO;
+
+
+entity FIFO is
+  port (
+    I_WR_EN : in  std_logic;
+    I_DATA  : out std_logic_vector(31 downto 0);
+    I_RD_EN : in  std_logic;
+    O_DATA  : out std_logic_vector(31 downto 0)
+  -- synthesis translate_off
+  );
+end entity FIFO;
+

vsg/tests/port/rule_014_test_input.vhd

@@ -16,3 +16,15 @@ entity FIFO is
     I_RD_EN : in  std_logic;
     O_DATA  : out std_logic_vector(31 downto 0));
 end entity FIFO;
+
+
+entity FIFO is
+  port (
+    I_WR_EN : in  std_logic;
+    I_DATA  : out std_logic_vector(31 downto 0);
+    I_RD_EN : in  std_logic;
+    O_DATA  : out std_logic_vector(31 downto 0)
+  -- synthesis translate_off
+  );
+end entity FIFO;
+

vsg/tests/process/rule_039_test_input.fixed.vhd

@@ -15,4 +15,9 @@ begin
 
   postponed process begin end process;
 
+
+  PROC_LABEL : postponed
+  -- synthesis translate_off
+  process begin end process;
+
 end;

vsg/tests/process/rule_039_test_input.vhd

@@ -15,4 +15,9 @@ begin
 
   process begin end process;
 
+
+  PROC_LABEL : postponed
+  -- synthesis translate_off
+  process begin end process;
+
 end;

vsg/tests/type_definition/rule_018_test_input.fixed.vhd

@@ -13,6 +13,16 @@ architecture RTL of FIFO is
 
   (idle, write, read, done);
 
+  -- Honor comments
+
+  type state_machine is
+  -- some comment
+  (idle, write, read, done);
+
+  type state_machine
+  -- synthesis translate_off
+  is (idle, write, read, done);
+
 begin
 
 end architecture RTL;

vsg/tests/type_definition/rule_018_test_input.vhd

@@ -13,6 +13,16 @@ architecture RTL of FIFO is
 
   is (idle, write, read, done);
 
+  -- Honor comments
+
+  type state_machine
+  -- some comment
+  is (idle, write, read, done);
+
+  type state_machine
+  -- synthesis translate_off
+  is (idle, write, read, done);
+
 begin
 
 end architecture RTL;

vsg/tests/type_definition/test_rule_018.py

@@ -30,7 +30,7 @@ def test_rule_018(self):
         self.assertEqual(oRule.name, 'type')
         self.assertEqual(oRule.identifier, '018')
 
-        lExpected = [8, 11]
+        lExpected = [8, 11, 18]
 
         oRule.analyze(self.oFile)
         self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))

vsg/token/pragma.py

@@ -11,10 +11,10 @@ def __init__(self, sString):
         parser.item.__init__(self, sString)
 
 
-class pragma(parser.item):
+class pragma(parser.comment):
     '''
     unique_id = pragma : pragma
     '''
 
     def __init__(self, sString):
-        parser.item.__init__(self, sString)
+        parser.comment.__init__(self, sString)

vsg/token_map.py

@@ -3,6 +3,7 @@
 import pprint
 
 from vsg import parser
+from vsg import token
 
 
 class New():
@@ -123,6 +124,8 @@ def is_token_at_index_whitespace(self, iIndex):
     def is_token_at_index_whitespace_or_comment(self, iIndex):
         if self.is_token_at_index(parser.whitespace, iIndex):
             return True
+        if self.is_token_at_index(token.pragma.pragma, iIndex):
+            return True
         if self.is_token_at_index(parser.comment, iIndex):
             return True
         if self.is_token_at_index(parser.carriage_return, iIndex):