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@pkazanzides pkazanzides released this 07 May 00:32
Rev9
853301d

9.0 (2024-05-06)

  • FPGA V3:
    • Implemented 4-port Ethernet switch, with two ports for external RJ45 connectors (Eth1 and Eth2), one port for Zynq ARM processor (PS), and one port for real-time interface in FPGA (PL).
      • Currently supports only 1GB Ethernet connections
    • Support Ethernet-only network, via daisy-chain connection to all FPGA boards, with all protocols, including sequential-read-broadcast-write and broadcast-query-read-write
      • Uses board-id instead of FireWire node-id
      • Hub FPGA sends broadcast read response when all data ready (does not require block read from host PC)
      • Broadcast read response can have board data in any order (no longer sequential by board number)
    • Supports Ethernet/FireWire bridge, with all protocols
    • Complete interface (i.e., quadlet and block, read and write) from PS to FPGA registers via EMIO (Version 1).
    • Revised Ethernet status/control register (12)
      • Can enable/disable PS connection to Ethernet switch (initially disabled, enabled by embedded software during initialization)
  • FPGA V3 and V2:
    • Board number is automatically added to lsb of IP address
    • Support UDP multicast (address 224.0.0.100), including for broadcast-write protocols
    • Send raw Ethernet multicast packets when IP address assigned (to initialize Ethernet switches) and for publishing data in broadcast-query-read-write protocol.
    • Improved arbitration between FireWire, Ethernet and Zynq EMIO (FPGA V3 only) for FPGA internal busses.
    • Separate timestamps for FireWire, Ethernet and Zynq EMIO (FPGA V3 only) interfaces
  • FPGA V2:
    • Limited support for all protocols on Ethernet-only network (FPGA V2 has only one Ethernet port)
  • All FPGA Versions (V1, V2, V3):
    • Added register 15, which contains build information based on git describe
    • Added reg_rwait to indicate whether read bus requires 0 or 1 wait-states when reading data
    • Design improvements, including simplification of internal busses
    • Removed xise project files; only support building with CMake and Xilinx ISE command line tools
    • Removed many obsolete files from repository, including Generated directory (use GitHub Releases instead).
  • DRAC (dVRK-Si):
    • Corrected error in ECM encoder preload
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