Add vbitclr

README.md

@@ -162,8 +162,6 @@ Vector Multiplication High
 
 ### vssrarn.bu.h/hu.w/wu.d
 
-### vbitclr.b/h/w/d
-
 ### vbitset.b/h/w/d
 
 ### vbitrev.b/h/w/d
@@ -366,8 +364,6 @@ Vector Multiplication High
 
 ### vextl.qu.du
 
-### vbitclri.b/h/w/d
-
 ### vbitseti.b/h/w/d
 
 ### vbitrevi.b/h/w/d

code/common.h

@@ -24,8 +24,12 @@ union v128 {
   __m128i m128i;
   __m128 m128;
   __m128d m128d;
+  v2i64 __v2i64;
+  v2u64 __v2u64;
   v4i32 __v4i32;
+  v4u32 __v4u32;
   v8i16 __v8i16;
+  v8u16 __v8u16;
   v16i8 __v16i8;
   v16u8 __v16u8;
 
@@ -43,8 +47,13 @@ union v128 {
   }
 
   operator __m128i() { return m128i; }
+  // duplicate with __m128i
+  // operator v2i64() { return __v2i64; }
+  operator v2u64() { return __v2u64; }
   operator v4i32() { return __v4i32; }
+  operator v4u32() { return __v4u32; }
   operator v8i16() { return __v8i16; }
+  operator v8u16() { return __v8u16; }
   operator v16i8() { return __v16i8; }
   operator v16u8() { return __v16u8; }
   bool operator==(const v128 &other) const {

code/gen_impl.py

@@ -95,4 +95,22 @@
             )
             print(f"}}", file=f)
 
-os.system("clang-format -i *.cpp *.h")
+for width in ["b", "h", "w", "d"]:
+    w = widths[width]
+    m = members[width]
+    with open(f"vbitclr_{width}.h", "w") as f:
+        print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
+        print(
+            f"  dst.{m}[i] = a.{m}[i] & (~((u{w})1 << (b.{m}[i] % {w})));",
+            file=f,
+        )
+        print(f"}}", file=f)
+    with open(f"vbitclri_{width}.h", "w") as f:
+        print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
+        print(
+            f"  dst.{m}[i] = a.{m}[i] & (~((u{w})1 << imm));",
+            file=f,
+        )
+        print(f"}}", file=f)
+
+os.system("clang-format -i *.cpp *.h")

code/gen_tb.py

@@ -1,5 +1,6 @@
 import os
 
+widths_signed = ["b", "h", "w", "d"]
 widths_all = ["b", "bu", "h", "hu", "w", "wu", "d", "du"]
 widths_vaddw = [
     "h_b",
@@ -17,10 +18,13 @@
 ]
 
 tb = {
+    # widths, args, extra args for imm
     "vavg": (widths_all, "v128 a, v128 b"),
     "vavgr": (widths_all, "v128 a, v128 b"),
     "vaddwev": (widths_vaddw, "v128 a, v128 b"),
     "vaddwod": (widths_vaddw, "v128 a, v128 b"),
+    "vbitclr": (widths_signed, "v128 a, v128 b"),
+    "vbitclri": (widths_signed, "v128 a, int imm", [0, 3, 7]),
 }
 
 for name in tb:
@@ -47,7 +51,11 @@
             print("}", file=f)
             print("", file=f)
             print("void test() {", file=f)
-            print(f"  FUZZ{fuzz_args}({inst_name});", file=f)
+            if len(t) >= 3:
+                for imm in t[2]:
+                    print(f"  FUZZ{fuzz_args}({inst_name}, {imm});", file=f)
+            else:
+                print(f"  FUZZ{fuzz_args}({inst_name});", file=f)
             print("}", file=f)
 
 os.system("clang-format -i *.cpp *.h")

code/vbitclr_b.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vbitclr_b(v128 a, v128 b) {
+  v128 dst;
+#include "vbitclr_b.h"
+  return dst;
+}
+
+void test() { FUZZ2(vbitclr_b); }

code/vbitclr_b.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 16; i++) {
+  dst.byte[i] = a.byte[i] & (~((u8)1 << (b.byte[i] % 8)));
+}

code/vbitclr_d.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vbitclr_d(v128 a, v128 b) {
+  v128 dst;
+#include "vbitclr_d.h"
+  return dst;
+}
+
+void test() { FUZZ2(vbitclr_d); }

code/vbitclr_d.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 2; i++) {
+  dst.dword[i] = a.dword[i] & (~((u64)1 << (b.dword[i] % 64)));
+}

code/vbitclr_h.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vbitclr_h(v128 a, v128 b) {
+  v128 dst;
+#include "vbitclr_h.h"
+  return dst;
+}
+
+void test() { FUZZ2(vbitclr_h); }

code/vbitclr_h.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 8; i++) {
+  dst.half[i] = a.half[i] & (~((u16)1 << (b.half[i] % 16)));
+}

code/vbitclr_w.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vbitclr_w(v128 a, v128 b) {
+  v128 dst;
+#include "vbitclr_w.h"
+  return dst;
+}
+
+void test() { FUZZ2(vbitclr_w); }

code/vbitclr_w.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 4; i++) {
+  dst.word[i] = a.word[i] & (~((u32)1 << (b.word[i] % 32)));
+}

code/vbitclri_b.cpp

@@ -0,0 +1,13 @@
+#include "common.h"
+
+v128 vbitclri_b(v128 a, int imm) {
+  v128 dst;
+#include "vbitclri_b.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vbitclri_b, 0);
+  FUZZ1(vbitclri_b, 3);
+  FUZZ1(vbitclri_b, 7);
+}

code/vbitclri_b.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 16; i++) {
+  dst.byte[i] = a.byte[i] & (~((u8)1 << imm));
+}

code/vbitclri_d.cpp

@@ -0,0 +1,13 @@
+#include "common.h"
+
+v128 vbitclri_d(v128 a, int imm) {
+  v128 dst;
+#include "vbitclri_d.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vbitclri_d, 0);
+  FUZZ1(vbitclri_d, 3);
+  FUZZ1(vbitclri_d, 7);
+}

code/vbitclri_d.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 2; i++) {
+  dst.dword[i] = a.dword[i] & (~((u64)1 << imm));
+}

code/vbitclri_h.cpp

@@ -0,0 +1,13 @@
+#include "common.h"
+
+v128 vbitclri_h(v128 a, int imm) {
+  v128 dst;
+#include "vbitclri_h.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vbitclri_h, 0);
+  FUZZ1(vbitclri_h, 3);
+  FUZZ1(vbitclri_h, 7);
+}

code/vbitclri_h.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 8; i++) {
+  dst.half[i] = a.half[i] & (~((u16)1 << imm));
+}

code/vbitclri_w.cpp

@@ -0,0 +1,13 @@
+#include "common.h"
+
+v128 vbitclri_w(v128 a, int imm) {
+  v128 dst;
+#include "vbitclri_w.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vbitclri_w, 0);
+  FUZZ1(vbitclri_w, 3);
+  FUZZ1(vbitclri_w, 7);
+}

code/vbitclri_w.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 4; i++) {
+  dst.word[i] = a.word[i] & (~((u32)1 << imm));
+}

docs/lsx_bitops/vbitsel.md → docs/lsx_bitops/vbitwise.md

@@ -1,4 +1,4 @@
-# Bitwise Selection
+# Bitwise Operations
 
 ## __m128i __lsx_vbitsel_v (__m128i a, __m128i b, __m128i c)
 
@@ -20,3 +20,13 @@ Compute bitwise selection: for each bit position, if the bit in `c` equals to on
 ```c++
 {% include 'vbitsel_v.h' %}
 ```
+
+{{ vbitclr('b') }}
+{{ vbitclr('h') }}
+{{ vbitclr('w') }}
+{{ vbitclr('d') }}
+
+{{ vbitclri('b') }}
+{{ vbitclri('h') }}
+{{ vbitclri('w') }}
+{{ vbitclri('d') }}

main.py

@@ -156,6 +156,25 @@ def vavgr(name):
             desc=f"Compute the average (rounded towards positive infinity) of {signedness} {width}-bit elements in `a` and `b`, save the result in `dst`.",
         )
 
+    @env.macro
+    def vbitclr(name):
+        width = widths[name]
+        return instruction(
+            intrinsic=f"__m128i __lsx_vbitclr_{name} (__m128i a, __m128i b)",
+            instr=f"vbitclr.{name} vr, vr, vr",
+            desc=f"Clear the bit specified by elements in `b` from {width}-bit elements in `a`, save the result in `dst`.",
+        )
+
+    @env.macro
+    def vbitclri(name):
+        width = widths[name]
+        imm_upper = width - 1
+        return instruction(
+            intrinsic=f"__m128i __lsx_vbitclri_{name} (__m128i a, imm0_{imm_upper} imm)",
+            instr=f"vbitclri.{name} vr, vr, imm",
+            desc=f"Clear the bit specified by `imm` from {width}-bit elements in `a`, save the result in `dst`.",
+        )
+
     @env.macro
     def vshuf_hwd(name):
         width = widths[name]