Add vadda

README.md

@@ -83,10 +83,6 @@ Vector Half Add Unsigned
 
 Vector Half Sub Unsigned
 
-### vadda.b/h/w/d
-
-Vector Add Absolute
-
 ### vavg.b/h/w/d
 
 Vector Average

code/vadda_b.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 16; i++) {
+  dst.byte[i] = abs(a.byte[i]) + abs(b.byte[i]);
+}

code/vadda_d.h

@@ -0,0 +1,4 @@
+for (int i = 0; i < 2; i++) {
+  dst.dword[i] = abs(a.dword[i]) + abs(b.dword[i]);
+}
+

code/vadda_h.h

@@ -0,0 +1,4 @@
+for (int i = 0; i < 8; i++) {
+  dst.half[i] = abs(a.half[i]) + abs(b.half[i]);
+}
+

code/vadda_w.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 4; i++) {
+  dst.word[i] = abs(a.word[i]) + abs(b.word[i]);
+}

docs/lsx_integer/vaddsub.md

@@ -1,4 +1,4 @@
-# Add/Subtract/Absolute Difference
+# Add/Subtract/Absolute
 
 {{ vadd('b') }}
 {{ vadd('h') }}
@@ -14,3 +14,8 @@
 {{ vabsd('wu') }}
 {{ vabsd('d') }}
 {{ vabsd('du') }}
+
+{{ vadda('b') }}
+{{ vadda('h') }}
+{{ vadda('w') }}
+{{ vadda('d') }}

main.py

@@ -91,3 +91,12 @@ def vldrepl(name):
             instr=f"vldrepl.{name} vr, r, imm",
             desc=f"Read {width}-bit data from memory address `addr + (offset << {shift})`, replicate the data to all vector lanes and save into `dst`.",
         )
+
+    @env.macro
+    def vadda(name):
+        width = widths[name]
+        return instruction(
+            intrinsic=f"__m128i __lsx_vadda_{name} (__m128i a, __m128i b)",
+            instr=f"vadda.{name} vr, vr, vr",
+            desc=f"Add absolute of {width}-bit elements in `a` and `b`, save the result in `dst`.",
+        )