GitHub - jpy794/very-simple-cpu: A synthesizable 5-stage pipeline RISC-V CPU for COD course of USTC.

jpy794 / very-simple-cpu Public

A synthesizable 5-stage pipeline RISC-V CPU for COD course of USTC.

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
itf		itf
perip		perip
pkg		pkg
tb		tb
util		util
Alu.sv		Alu.sv
Branch.sv		Branch.sv
BusCtrl.sv		BusCtrl.sv
Cpu.sv		Cpu.sv
DataCache.sv		DataCache.sv
Decoder.sv		Decoder.sv
InsCache.sv		InsCache.sv
Register.sv		Register.sv
Top.sv		Top.sv
tb_Top.sv		tb_Top.sv