Add rule for preprocessor directives in SystemVerilog

jwortmann · Oct 1, 2020 · bd12968 · bd12968
1 parent 9b3b650
commit bd12968
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diff --git a/Brackets Dark.sublime-color-scheme b/Brackets Dark.sublime-color-scheme
@@ -1462,6 +1462,12 @@
             "scope": "source.swift storage.type.decorator",
             "foreground": "var(pink)"
         },
+        // SystemVerilog specific rules >> https://packagecontrol.io/packages/SystemVerilog
+        {
+            "name": "SystemVerilog preprocessor directive",
+            "scope": "constant.other.preprocessor.systemverilog",
+            "foreground": "var(purple)"
+        },
         // Textile specific rules
         {
             "name": "Textile link title",

diff --git a/Brackets Light.sublime-color-scheme b/Brackets Light.sublime-color-scheme
@@ -1462,6 +1462,12 @@
             "scope": "source.swift storage.type.decorator",
             "foreground": "var(pink)"
         },
+        // SystemVerilog specific rules >> https://packagecontrol.io/packages/SystemVerilog
+        {
+            "name": "SystemVerilog preprocessor directive",
+            "scope": "constant.other.preprocessor.systemverilog",
+            "foreground": "var(purple)"
+        },
         // Textile specific rules
         {
             "name": "Textile link title",