- fsic-sim – FSIC Simulation Environment
- fsic-sim (individual)
- fsic-plus – FSIC Improvement ( team )
- catapult-hls – Catapult HLS tool setup / HLS
- catapult-fir (individual)
- catapult-edgedetect (team)
- snp-flow – Synopsys Front end and Back-end (team)
- fsic-fpga – Caravel-FSIC + FPGA-FSIC + DMA (team)
- hls-ap - HLS Application Accelerator – Kernel (team)
- fsic-final – FSIC Final Project – FPGA & ASIC flow (team)
- snp-lp – lower power design
- snp-dft – design for testing
- Vitis/Vivado/Vitis HLS Software 2022.1
- Simens/Mentor Catapult/QuestaSim - Access from ICLab
- Synopsys - Access from ICLab
- Design Compiler
- ICC2
- IC-Validator
- Star-RC
- Primetime