Remove wire logic

leonardt · Nov 16, 2023 · b7b5665 · b7b5665
1 parent e997c4f
commit b7b5665
Showing 1 changed file with 2 additions and 5 deletions.
diff --git a/tests/test_property.py b/tests/test_property.py
@@ -11,8 +11,8 @@
 
 def requires_ncsim(test_fn):
     def wrapper(test_fn, *args, **kwargs):
-        if not shutil.which("ncsim"):
-            return pytest.skip("need ncsim for SVA test")
+        # if not shutil.which("ncsim"):
+        #     return pytest.skip("need ncsim for SVA test")
         return test_fn(*args, **kwargs)
     return decorator.decorator(wrapper, test_fn)
 
@@ -558,9 +558,6 @@ class Main(m.Circuit):
     # Should not fail with no ASSERT_ON
     tester.compile_and_run("system-verilog", simulator="ncsim",
                            flags=["-sv"], magma_output="mlir-verilog")
-    # Check that wire prefix is generated properly
-    with open("build/Main.v", "r") as file_:
-        assert "wire _FAULT_ASSERT_WIRE_0" in file_.read()
     # Should fail
     with pytest.raises(AssertionError):
         if isinstance(compile_guard, str):