Libre Silicon v0.1

This is the LibreSilicon process specification (WIP) Please use XeLaTeX for rendering the documents

Features are:

• 1 micron (1 um)
• twin-well for cmos
• pbase / nbase (optional) for bipolar
• shallow trench isolation
• sonos for flash (optional)
• silicification

aiming higher voltages, higher speed and higher feasibilty for modern Analog and System-on-Chip design.