ALU - ADD/SUB/CMP

👨‍💻 Group Members

Name	NetID
Guangxuan Li	gl137
Zhigang Wei	zw261

📝 Description

Module tree:

alu
├───addsub
│   └───myPPA
│       ├───prefix_network_SK   -- Sklansky: even faster
│       │   └───op_o
│       ├───//prefix_network_KS -- Kogge-Stone: better delay
│       │   └───op_o
│       └───//prefix_network_BK -- Brent-Kung: high delay, deprecated
│           └───op_o
├───lt
├───ne
├───bitwise_and
├───bitwise_or
├───sll
└───sra

• alu.v: top level entity, selects out from submodules according to opcode.

• prefix_network_*.v: we implemented and tested Brent-Kung, Kogge-Stone and Sklansky prefix carry generation networks. After gate level simulation and fitting, we decided to use Sklansky adder for its low latency and low LUT usage. You can comment and uncomment the code in myPPA.v to change between those implementations.

• myPPA.v: a adder with two integer inputs, a sum output, a Carry-in, a Carry-out(treating inputs as unsigned), and a overflow(treating inputs as signed) output.

• addsub.v: added some logics around the adder to invert the input B to achieve subtraction operation.

• lt.v: uses the sign bit from subtraction result and overflow flag to decide if A is less than B.

• ne.v: compares A and B bit-by-bit to determine if they are not equal.

• bitwise_and.v: not implemented yet, dummy code.

• bitwise_or.v: not implemented yet, dummy code.

• sll.v: logical shift left.

• sra.v: arithetic shift right.

🐞 Bugs and Issues

Nothing at the moment.