Test

Support last stage pass-gate-logic model for MUX circuit model #6090

Job	Run time
Detect code changes	8s
Build w/o Yosys (Ubuntu 22.04)	20m 1s
Build w/o Yosys plugin (Ubuntu 22.04)	34m 31s
Build Compatibility: GCC-9 (Ubuntu 22.04)	35m 25s
Build w/o test (Ubuntu 22.04)	36m 56s
No-warning Build (Ubuntu 22.04)	35m 28s
Build w/o version number (Ubuntu 22.04)	35m 33s
Build Compatibility: GCC-10 (Ubuntu 22.04)	37m 30s
Debug Build (Ubuntu 22.04)	28m 20s
Build w/o SWIG support (Ubuntu 22.04)	35m 3s
Build Compatibility: GCC-11 (Ubuntu 22.04)	36m 3s
Build Compatibility: GCC-12 (Ubuntu 22.04)	39m 46s
Build Compatibility: Clang-11 (Ubuntu 22.04)	39m 52s
Build (GCC-11 on Ubuntu 20.04)	37m 20s
docker_regression_tests	0s
Build Compatibility: Clang-12 (Ubuntu 22.04)	39m 22s
Build (Clang-10 on Ubuntu 20.04)	34m 37s
Build Compatibility: Clang-13 (Ubuntu 22.04)	39m 49s
Build Compatibility: Clang-14 (Ubuntu 22.04)	29m 14s
Build docker image for distribution	31s
linux_regression_tests (basic_reg_yosys_only_test)	18s
linux_regression_tests (basic_reg_test)	5m 43s
linux_regression_tests (fpga_verilog_reg_test)	5m 44s
linux_regression_tests (fpga_bitstream_reg_test)	5m 42s
linux_regression_tests (fpga_sdc_reg_test)	20s
linux_regression_tests (fpga_spice_reg_test)	26s
linux_regression_tests (micro_benchmark_reg_test)	4m 13s
linux_regression_tests (quicklogic_reg_test)	5m 41s
linux_regression_tests (vtr_benchmark_reg_test)	5m 43s
linux_regression_tests (iwls_benchmark_reg_test)	5m 42s
linux_regression_tests (tcl_reg_test)	20s
	10h 35m 21s

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