Test

Bump vtr-verilog-to-routing from `876311a` to `6ce3706` #6170

Job	Run time
Detect code changes	7s
Debug Build (Ubuntu 22.04)	30m 59s
Build w/o Yosys (Ubuntu 22.04)	16m 8s
Build Compatibility: GCC-9 (Ubuntu 22.04)	35m 46s
Build w/o Yosys plugin (Ubuntu 22.04)	32m 8s
docker_regression_tests	0s
Build Compatibility: GCC-10 (Ubuntu 22.04)	37m 2s
Build w/o test (Ubuntu 22.04)	31m 2s
No-warning Build (Ubuntu 22.04)	30m 47s
Build Compatibility: GCC-11 (Ubuntu 22.04)	32m 8s
Build w/o version number (Ubuntu 22.04)	32m 4s
Build Compatibility: GCC-12 (Ubuntu 22.04)	41m 7s
Build (GCC-11 on Ubuntu 20.04)	45m 9s
Build w/o SWIG support (Ubuntu 22.04)	35m 18s
Build Compatibility: Clang-11 (Ubuntu 22.04)	39m 12s
Build (Clang-10 on Ubuntu 20.04)	36m 53s
Build Compatibility: Clang-12 (Ubuntu 22.04)	41m 8s
Build Compatibility: Clang-13 (Ubuntu 22.04)	40m 39s
Build Compatibility: Clang-14 (Ubuntu 22.04)	40m 40s
Build docker image for distribution	26s
linux_regression_tests (basic_reg_yosys_only_test)	28s
linux_regression_tests (basic_reg_test)	18m 58s
linux_regression_tests (fpga_verilog_reg_test)	8m 9s
linux_regression_tests (fpga_bitstream_reg_test)	13m 4s
linux_regression_tests (fpga_sdc_reg_test)	23s
linux_regression_tests (fpga_spice_reg_test)	20s
linux_regression_tests (micro_benchmark_reg_test)	3m 47s
linux_regression_tests (quicklogic_reg_test)	13m 52s
linux_regression_tests (vtr_benchmark_reg_test)	10m 40s
linux_regression_tests (iwls_benchmark_reg_test)	11m 34s
linux_regression_tests (tcl_reg_test)	27s
	11h 20m 25s

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