Merge pull request #1366 from lnis-uofu/xt_tile_module_port #2396
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| name: Cell Library Tests | |
| # Run CI on push, PR, and weekly. | |
| on: | |
| push: | |
| pull_request: | |
| schedule: | |
| - cron: "0 0 * * 0 " # weekly | |
| # Multiple job to tests | |
| jobs: | |
| # Test the RTL compilation compatibility | |
| verilog: | |
| name: RTL compilation and tests | |
| runs-on: ubuntu-22.04 | |
| steps: | |
| - name: Cancel previous | |
| uses: styfle/[email protected] | |
| with: | |
| access_token: ${{ github.token }} | |
| - name: Checkout OpenFPGA repo | |
| uses: actions/checkout@v3 | |
| - name: Install Dependencies | |
| run: | | |
| sudo bash .github/workflows/install_dependencies_run_ubuntu22p04.sh | |
| - name: Dump tool versions | |
| run: | | |
| iverilog -V | |
| vvp -V | |
| - name: Verilog compilation | |
| run: | | |
| cd openfpga_flow/openfpga_cell_library | |
| make compile_verilog |