[core] code format

lnis-uofu · Sep 26, 2023 · 1624dc9 · 1624dc9
1 parent 76f446c
commit 1624dc9
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Showing 4 changed files with 8 additions and 7 deletions.
diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp
@@ -113,10 +113,10 @@ void add_grid_module_duplicated_pb_type_ports(
             /* If the port is required to be merged, we deposit zero as subtile
              * index */
             if (tile_annotation.is_tile_port_to_merge(
-                  std::string(grid_type_descriptor->name), pin_info.get_name())) {
+                  std::string(grid_type_descriptor->name),
+                  pin_info.get_name())) {
               if (subtile_index == 0) {
-                port_name = generate_grid_port_name(
-                  0, 0, 0, TOP, pin_info);
+                port_name = generate_grid_port_name(0, 0, 0, TOP, pin_info);
               } else {
                 continue;
               }

diff --git a/openfpga/src/fabric/build_grid_module_utils.cpp b/openfpga/src/fabric/build_grid_module_utils.cpp
@@ -97,8 +97,7 @@ void add_grid_module_net_connect_pb_graph_pin(
     if (tile_annotation.is_tile_port_to_merge(
           std::string(grid_type_descriptor->name), pin_info.get_name())) {
       /* Exception: use top side for these merged ports */
-      grid_port_name = generate_grid_port_name(
-        0, 0, 0, TOP, pin_info);
+      grid_port_name = generate_grid_port_name(0, 0, 0, TOP, pin_info);
       VTR_LOG("Use source pin '%s'\n", grid_port_name.c_str());
     }
     ModulePortId grid_module_port_id =

diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp
@@ -1407,7 +1407,8 @@ static int build_top_module_global_net_for_given_tile_module(
           if (tile_annotation.is_tile_port_to_merge(
                 std::string(physical_tile->name), grid_pin_info.get_name())) {
             if (subtile_index != 0) {
-              grid_port_name = generate_grid_port_name(0, 0, 0, TOP, grid_pin_info);
+              grid_port_name =
+                generate_grid_port_name(0, 0, 0, TOP, grid_pin_info);
             } else {
               continue;
             }

diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp
@@ -953,7 +953,8 @@ static int build_top_module_global_net_for_given_grid_module(
           if (tile_annotation.is_tile_port_to_merge(
                 std::string(physical_tile->name), grid_pin_info.get_name())) {
             if (subtile_index != 0) {
-              grid_port_name = generate_grid_port_name(0, 0, 0, TOP, grid_pin_info);
+              grid_port_name =
+                generate_grid_port_name(0, 0, 0, TOP, grid_pin_info);
             } else {
               continue;
             }