[test] developing new test to increase coverage on module renaming

openfpga_flow/regression_test_scripts/basic_reg_test.sh

@@ -206,6 +206,7 @@ echo -e "Module naming";
 run-task basic_tests/module_naming/using_index $@
 run-task basic_tests/module_naming/renaming_rules $@
 run-task basic_tests/module_naming/renaming_rules_strong $@
+run-task basic_tests/module_naming/renaming_rules_on_indexed_names $@
 
 echo -e "Testing global port definition from tiles";
 run-task basic_tests/global_tile_ports/global_tile_clock $@

openfpga_flow/tasks/basic_tests/module_naming/renaming_rules_on_indexed_names/config/module_names.xml

@@ -0,0 +1,12 @@
+<module_names>
+  <module_name default="mux_tree_tapbuf_size10_mem" given="mux_tree_mem_max"/>
+  <module_name default="mux_tree_size_2" given="mux_tree_mini"/>
+  <module_name default="logical_tile_clb_mode_clb_" given="logical_tile_clb_mode_clb_unique"/>
+  <module_name default="sb_1__1_" given="sb_max"/>
+  <module_name default="cby_1__1_" given="cby_max"/>
+  <module_name default="cbx_1__1_" given="cbx_max"/>
+  <module_name default="tile_1__1_" given="tile_clb"/>
+  <module_name default="tile_2__1_" given="tile_dsp"/>
+  <module_name default="fpga_core" given="pfabric_core"/>
+  <module_name default="fpga_top" given="pfabric_top"/>
+</module_names>

openfpga_flow/tasks/basic_tests/module_naming/renaming_rules_on_indexed_names/config/task.conf

@@ -0,0 +1,51 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/module_rename_preconfig_testbench_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+openfpga_vpr_extra_options=--constant_net_method route --skip_sync_clustering_and_routing_results on
+openfpga_pb_pin_fixup_command = pb_pin_fixup --verbose
+openfpga_vpr_device=3x2
+openfpga_vpr_route_chan_width=60
+openfpga_group_tile_config_option=--group_tile ${PATH:TASK_DIR}/config/tile_config.xml
+openfpga_verilog_testbench_options=
+openfpga_add_fpga_core_module=add_fpga_core_to_fabric --instance_name fpga_core_inst
+openfpga_fabric_module_name_options=--name_module_using_index
+openfpga_rename_module_file = ${PATH:TASK_DIR}/config/module_names.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v
+
+[SYNTHESIS_PARAM]
+# Yosys script parameters
+bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v
+bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v
+bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8
+bench_read_verilog_options_common = -nolatches
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
+
+bench0_top = mac_8
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

openfpga_flow/tasks/basic_tests/module_naming/renaming_rules_on_indexed_names/config/tile_config.xml

@@ -0,0 +1 @@
+<tiles style="top_left"/>