[core] code format

openfpga/src/base/openfpga_verilog_template.h

@@ -138,8 +138,7 @@ int write_full_testbench_template(const T& openfpga_ctx, const Command& cmd,
     g_vpr_ctx.atom(), g_vpr_ctx.placement(), pin_constraints, bus_group,
     cmd_context.option_value(cmd, opt_bitstream),
     openfpga_ctx.io_location_map(), openfpga_ctx.io_name_map(),
-    openfpga_ctx.module_name_map(),
-    openfpga_ctx.fabric_global_port_info(),
+    openfpga_ctx.module_name_map(), openfpga_ctx.fabric_global_port_info(),
     openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.arch().circuit_lib,
     openfpga_ctx.simulation_setting(), openfpga_ctx.arch().config_protocol,
     options);
@@ -213,8 +212,7 @@ int write_preconfigured_fabric_wrapper_template(
     openfpga_ctx.module_graph(), openfpga_ctx.bitstream_manager(),
     g_vpr_ctx.atom(), g_vpr_ctx.placement(), pin_constraints, bus_group,
     openfpga_ctx.io_location_map(), openfpga_ctx.io_name_map(),
-    openfpga_ctx.module_name_map(),
-    openfpga_ctx.fabric_global_port_info(),
+    openfpga_ctx.module_name_map(), openfpga_ctx.fabric_global_port_info(),
     openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.arch().circuit_lib,
     openfpga_ctx.arch().config_protocol, options);
 }
@@ -275,7 +273,8 @@ int write_mock_fpga_wrapper_template(const T& openfpga_ctx, const Command& cmd,
   return fpga_verilog_mock_fpga_wrapper(
     openfpga_ctx.module_graph(), g_vpr_ctx.atom(), g_vpr_ctx.placement(),
     pin_constraints, bus_group, openfpga_ctx.io_location_map(),
-    openfpga_ctx.io_name_map(), openfpga_ctx.module_name_map(), openfpga_ctx.fabric_global_port_info(),
+    openfpga_ctx.io_name_map(), openfpga_ctx.module_name_map(),
+    openfpga_ctx.fabric_global_port_info(),
     openfpga_ctx.vpr_netlist_annotation(), options);
 }
 

openfpga/src/fpga_verilog/verilog_api.cpp

@@ -105,7 +105,8 @@ int fpga_fabric_verilog(
    * logic generation is not possible!!!
    */
   print_verilog_submodule(module_manager, netlist_manager, blwl_sr_banks,
-                          mux_lib, decoder_lib, circuit_lib, module_name_map, submodule_dir_path,
+                          mux_lib, decoder_lib, circuit_lib, module_name_map,
+                          submodule_dir_path,
                           std::string(DEFAULT_SUBMODULE_DIR_NAME), options);
 
   /* Generate routing blocks */
@@ -142,12 +143,10 @@ int fpga_fabric_verilog(
   /* Generate FPGA fabric */
   print_verilog_core_module(netlist_manager,
                             const_cast<const ModuleManager &>(module_manager),
-                            module_name_map,
-                            src_dir_path, options);
+                            module_name_map, src_dir_path, options);
   print_verilog_top_module(netlist_manager,
                            const_cast<const ModuleManager &>(module_manager),
-                           module_name_map,
-                           src_dir_path, options);
+                           module_name_map, src_dir_path, options);
 
   /* Generate an netlist including all the fabric-related netlists */
   print_verilog_fabric_include_netlist(
@@ -176,8 +175,7 @@ int fpga_verilog_full_testbench(
   const AtomContext &atom_ctx, const PlacementContext &place_ctx,
   const PinConstraints &pin_constraints, const BusGroup &bus_group,
   const std::string &bitstream_file, const IoLocationMap &io_location_map,
-  const IoNameMap &io_name_map,
-  const ModuleNameMap& module_name_map,
+  const IoNameMap &io_name_map, const ModuleNameMap &module_name_map,
   const FabricGlobalPortInfo &fabric_global_port_info,
   const VprNetlistAnnotation &netlist_annotation,
   const CircuitLibrary &circuit_lib,
@@ -205,8 +203,7 @@ int fpga_verilog_full_testbench(
     module_manager, bitstream_manager, fabric_bitstream, blwl_sr_banks,
     circuit_lib, config_protocol, fabric_global_port_info, atom_ctx, place_ctx,
     pin_constraints, bus_group, bitstream_file, io_location_map, io_name_map,
-    module_name_map,
-    netlist_annotation, netlist_name, top_testbench_file_path,
+    module_name_map, netlist_annotation, netlist_name, top_testbench_file_path,
     simulation_setting, options);
 
   /* Generate a Verilog file including all the netlists that have been generated
@@ -228,8 +225,7 @@ int fpga_verilog_preconfigured_fabric_wrapper(
   const BitstreamManager &bitstream_manager, const AtomContext &atom_ctx,
   const PlacementContext &place_ctx, const PinConstraints &pin_constraints,
   const BusGroup &bus_group, const IoLocationMap &io_location_map,
-  const IoNameMap &io_name_map,
-  const ModuleNameMap &module_name_map,
+  const IoNameMap &io_name_map, const ModuleNameMap &module_name_map,
   const FabricGlobalPortInfo &fabric_global_port_info,
   const VprNetlistAnnotation &netlist_annotation,
   const CircuitLibrary &circuit_lib, const ConfigProtocol &config_protocol,
@@ -254,8 +250,8 @@ int fpga_verilog_preconfigured_fabric_wrapper(
   status = print_verilog_preconfig_top_module(
     module_manager, bitstream_manager, config_protocol, circuit_lib,
     fabric_global_port_info, atom_ctx, place_ctx, pin_constraints, bus_group,
-    io_location_map, io_name_map, module_name_map, netlist_annotation, netlist_name,
-    formal_verification_top_netlist_file_path, options);
+    io_location_map, io_name_map, module_name_map, netlist_annotation,
+    netlist_name, formal_verification_top_netlist_file_path, options);
 
   return status;
 }
@@ -268,8 +264,7 @@ int fpga_verilog_mock_fpga_wrapper(
   const ModuleManager &module_manager, const AtomContext &atom_ctx,
   const PlacementContext &place_ctx, const PinConstraints &pin_constraints,
   const BusGroup &bus_group, const IoLocationMap &io_location_map,
-  const IoNameMap &io_name_map,
-  const ModuleNameMap &module_name_map,
+  const IoNameMap &io_name_map, const ModuleNameMap &module_name_map,
   const FabricGlobalPortInfo &fabric_global_port_info,
   const VprNetlistAnnotation &netlist_annotation,
   const VerilogTestbenchOption &options) {
@@ -294,8 +289,8 @@ int fpga_verilog_mock_fpga_wrapper(
   std::string netlist_file_path = src_dir_path + netlist_file_name;
   status = print_verilog_mock_fpga_wrapper(
     module_manager, fabric_global_port_info, atom_ctx, place_ctx,
-    pin_constraints, bus_group, io_location_map, io_name_map,
-    module_name_map, netlist_annotation, netlist_name, netlist_file_path, options);
+    pin_constraints, bus_group, io_location_map, io_name_map, module_name_map,
+    netlist_annotation, netlist_name, netlist_file_path, options);
 
   /* Add fname to the netlist name list */
   NetlistId nlist_id = NetlistId::INVALID();

openfpga/src/fpga_verilog/verilog_api.h

@@ -56,8 +56,7 @@ int fpga_verilog_full_testbench(
   const AtomContext& atom_ctx, const PlacementContext& place_ctx,
   const PinConstraints& pin_constraints, const BusGroup& bus_group,
   const std::string& bitstream_file, const IoLocationMap& io_location_map,
-  const IoNameMap& io_name_map,
-  const ModuleNameMap& module_name_map,
+  const IoNameMap& io_name_map, const ModuleNameMap& module_name_map,
   const FabricGlobalPortInfo& fabric_global_port_info,
   const VprNetlistAnnotation& netlist_annotation,
   const CircuitLibrary& circuit_lib,
@@ -69,8 +68,7 @@ int fpga_verilog_preconfigured_fabric_wrapper(
   const BitstreamManager& bitstream_manager, const AtomContext& atom_ctx,
   const PlacementContext& place_ctx, const PinConstraints& pin_constraints,
   const BusGroup& bus_group, const IoLocationMap& io_location_map,
-  const IoNameMap& io_name_map,
-  const ModuleNameMap& module_name_map,
+  const IoNameMap& io_name_map, const ModuleNameMap& module_name_map,
   const FabricGlobalPortInfo& fabric_global_port_info,
   const VprNetlistAnnotation& netlist_annotation,
   const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol,
@@ -80,8 +78,7 @@ int fpga_verilog_mock_fpga_wrapper(
   const ModuleManager& module_manager, const AtomContext& atom_ctx,
   const PlacementContext& place_ctx, const PinConstraints& pin_constraints,
   const BusGroup& bus_group, const IoLocationMap& io_location_map,
-  const IoNameMap& io_name_map,
-  const ModuleNameMap& module_name_map,
+  const IoNameMap& io_name_map, const ModuleNameMap& module_name_map,
   const FabricGlobalPortInfo& fabric_global_port_info,
   const VprNetlistAnnotation& netlist_annotation,
   const VerilogTestbenchOption& options);

openfpga/src/fpga_verilog/verilog_decoders.cpp

@@ -52,8 +52,8 @@ static void print_verilog_mux_local_decoder_module(
   VTR_ASSERT(true == valid_file_stream(fp));
 
   /* TODO: create a name for the local encoder */
-  std::string module_name =
-    module_name_map.name(generate_mux_local_decoder_subckt_name(addr_size, data_size));
+  std::string module_name = module_name_map.name(
+    generate_mux_local_decoder_subckt_name(addr_size, data_size));
 
   /* Create a Verilog Module based on the circuit model, and add to module
    * manager */
@@ -181,9 +181,8 @@ static void print_verilog_mux_local_decoder_module(
 void print_verilog_submodule_mux_local_decoders(
   const ModuleManager& module_manager, NetlistManager& netlist_manager,
   const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib,
-  const ModuleNameMap& module_name_map,
-  const std::string& submodule_dir, const std::string& submodule_dir_name,
-  const FabricVerilogOption& options) {
+  const ModuleNameMap& module_name_map, const std::string& submodule_dir,
+  const std::string& submodule_dir_name, const FabricVerilogOption& options) {
   std::string verilog_fname(LOCAL_ENCODER_VERILOG_FILE_NAME);
   std::string verilog_fpath(submodule_dir + verilog_fname);
 
@@ -237,7 +236,8 @@ void print_verilog_submodule_mux_local_decoders(
   /* Generate Verilog modules for the found unique local encoders */
   for (const auto& decoder : decoder_lib.decoders()) {
     print_verilog_mux_local_decoder_module(fp, module_manager, decoder_lib,
-                                           decoder, module_name_map, options.default_net_type());
+                                           decoder, module_name_map,
+                                           options.default_net_type());
   }
 
   /* Close the file stream */
@@ -292,8 +292,8 @@ static void print_verilog_arch_decoder_module(
   VTR_ASSERT(true == valid_file_stream(fp));
 
   /* Create a name for the decoder */
-  std::string module_name =
-    module_name_map.name(generate_memory_decoder_subckt_name(addr_size, data_size));
+  std::string module_name = module_name_map.name(
+    generate_memory_decoder_subckt_name(addr_size, data_size));
 
   /* Create a Verilog Module based on the circuit model, and add to module
    * manager */
@@ -617,8 +617,8 @@ static void print_verilog_arch_decoder_with_data_in_module(
   VTR_ASSERT(true == valid_file_stream(fp));
 
   /* Create a name for the decoder */
-  std::string module_name =
-    module_name_map.name(generate_memory_decoder_with_data_in_subckt_name(addr_size, data_size));
+  std::string module_name = module_name_map.name(
+    generate_memory_decoder_with_data_in_subckt_name(addr_size, data_size));
 
   /* Create a Verilog Module based on the circuit model, and add to module
    * manager */
@@ -783,8 +783,8 @@ static void print_verilog_arch_decoder_with_data_in_module(
 void print_verilog_submodule_arch_decoders(
   const ModuleManager& module_manager, NetlistManager& netlist_manager,
   const DecoderLibrary& decoder_lib, const ModuleNameMap& module_name_map,
-  const std::string& submodule_dir,
-  const std::string& submodule_dir_name, const FabricVerilogOption& options) {
+  const std::string& submodule_dir, const std::string& submodule_dir_name,
+  const FabricVerilogOption& options) {
   std::string verilog_fname(ARCH_ENCODER_VERILOG_FILE_NAME);
   std::string verilog_fpath(submodule_dir + verilog_fname);
 
@@ -806,10 +806,12 @@ void print_verilog_submodule_arch_decoders(
   for (const auto& decoder : decoder_lib.decoders()) {
     if (true == decoder_lib.use_data_in(decoder)) {
       print_verilog_arch_decoder_with_data_in_module(
-        fp, module_manager, decoder_lib, decoder, module_name_map, options.default_net_type());
+        fp, module_manager, decoder_lib, decoder, module_name_map,
+        options.default_net_type());
     } else {
       print_verilog_arch_decoder_module(fp, module_manager, decoder_lib,
-                                        decoder, module_name_map, options.default_net_type());
+                                        decoder, module_name_map,
+                                        options.default_net_type());
     }
   }
 

openfpga/src/fpga_verilog/verilog_decoders.h

@@ -28,15 +28,14 @@ namespace openfpga {
 void print_verilog_submodule_mux_local_decoders(
   const ModuleManager& module_manager, NetlistManager& netlist_manager,
   const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib,
-  const ModuleNameMap& module_name_map,
-  const std::string& submodule_dir, const std::string& submodule_dir_name,
-  const FabricVerilogOption& options);
+  const ModuleNameMap& module_name_map, const std::string& submodule_dir,
+  const std::string& submodule_dir_name, const FabricVerilogOption& options);
 
 void print_verilog_submodule_arch_decoders(
   const ModuleManager& module_manager, NetlistManager& netlist_manager,
   const DecoderLibrary& decoder_lib, const ModuleNameMap& module_name_map,
-  const std::string& submodule_dir,
-  const std::string& submodule_dir_name, const FabricVerilogOption& options);
+  const std::string& submodule_dir, const std::string& submodule_dir_name,
+  const FabricVerilogOption& options);
 
 } /* end namespace openfpga */
 

openfpga/src/fpga_verilog/verilog_essential_gates.cpp

@@ -176,8 +176,8 @@ static void print_verilog_invbuf_module(
 
   /* Create a Verilog Module based on the circuit model, and add to module
    * manager */
-  ModuleId module_id =
-    module_manager.find_module(module_name_map.name(circuit_lib.model_name(circuit_model)));
+  ModuleId module_id = module_manager.find_module(
+    module_name_map.name(circuit_lib.model_name(circuit_model)));
   VTR_ASSERT(true == module_manager.valid_module_id(module_id));
 
   /* dump module definition + ports */
@@ -272,8 +272,8 @@ static void print_verilog_passgate_module(
 
   /* Create a Verilog Module based on the circuit model, and add to module
    * manager */
-  ModuleId module_id =
-    module_manager.find_module(module_name_map.name(circuit_lib.model_name(circuit_model)));
+  ModuleId module_id = module_manager.find_module(
+    module_name_map.name(circuit_lib.model_name(circuit_model)));
   VTR_ASSERT(true == module_manager.valid_module_id(module_id));
 
   /* dump module definition + ports */
@@ -468,8 +468,8 @@ static void print_verilog_gate_module(
 
   /* Create a Verilog Module based on the circuit model, and add to module
    * manager */
-  ModuleId module_id =
-    module_manager.find_module(module_name_map.name(circuit_lib.model_name(circuit_model)));
+  ModuleId module_id = module_manager.find_module(
+    module_name_map.name(circuit_lib.model_name(circuit_model)));
   VTR_ASSERT(true == module_manager.valid_module_id(module_id));
 
   /* dump module definition + ports */
@@ -509,12 +509,12 @@ static void print_verilog_gate_module(
  ***********************************************/
 static void print_verilog_constant_generator_module(
   const ModuleManager& module_manager, std::fstream& fp,
-  const size_t& const_value,
-  const ModuleNameMap& module_name_map,
+  const size_t& const_value, const ModuleNameMap& module_name_map,
   const e_verilog_default_net_type& default_net_type) {
   /* Find the module in module manager */
   std::string module_name = generate_const_value_module_name(const_value);
-  ModuleId const_val_module = module_manager.find_module(module_name_map.name(module_name));
+  ModuleId const_val_module =
+    module_manager.find_module(module_name_map.name(module_name));
   VTR_ASSERT(true == module_manager.valid_module_id(const_val_module));
 
   /* Ensure a valid file handler*/
@@ -568,11 +568,11 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager,
 
   /* Print constant generators */
   /* VDD */
-  print_verilog_constant_generator_module(module_manager, fp, 0,
-                                          module_name_map, options.default_net_type());
+  print_verilog_constant_generator_module(
+    module_manager, fp, 0, module_name_map, options.default_net_type());
   /* GND */
-  print_verilog_constant_generator_module(module_manager, fp, 1,
-                                          module_name_map, options.default_net_type());
+  print_verilog_constant_generator_module(
+    module_manager, fp, 1, module_name_map, options.default_net_type());
 
   for (const auto& circuit_model : circuit_lib.models()) {
     /* By pass user-defined modules */
@@ -581,12 +581,14 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager,
     }
     if (CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) {
       print_verilog_invbuf_module(module_manager, fp, circuit_lib,
-                                  circuit_model, module_name_map, options.default_net_type());
+                                  circuit_model, module_name_map,
+                                  options.default_net_type());
       continue;
     }
     if (CIRCUIT_MODEL_PASSGATE == circuit_lib.model_type(circuit_model)) {
       print_verilog_passgate_module(module_manager, fp, circuit_lib,
-                                    circuit_model, module_name_map, options.default_net_type());
+                                    circuit_model, module_name_map,
+                                    options.default_net_type());
       continue;
     }
     if (CIRCUIT_MODEL_GATE == circuit_lib.model_type(circuit_model)) {