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tangxifan committed Sep 27, 2023
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4 changes: 2 additions & 2 deletions docs/source/manual/arch_lang/annotate_vpr_arch.rst
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Expand Up @@ -85,7 +85,7 @@ For subtile port merge support (see an illustrative example in :numref:`fig_subt
.. _fig_subtile_port_merge:

.. figure:: ./figures/subtile_port_merge.png
:scale: 100%
:width: 100%
:alt: Difference in netlists with and without subtile port merging

Difference in netlists with and without subtile port merging
Expand Down Expand Up @@ -136,7 +136,7 @@ A more illustrative example:
.. _fig_global_tile_ports:

.. figure:: ./figures/global_tile_ports.png
:scale: 100%
:width: 100%
:alt: Difference between global port definition through circuit model and tile annotation

Difference between global port definition through circuit model and tile annotation
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