[core] code format

openfpga/src/base/openfpga_verilog_command_template.h

@@ -283,9 +283,11 @@ ShellCommandId add_write_testbench_template_command_template(
   shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
 
   /* add an option '--top_module'*/
-  CommandOptionId top_module_opt = shell_cmd.add_option(
-    "top_module", false,
-    "specify the top-level module name to be used in the testbench. Please avoid reserved words, i.e., fpga_top or fpga_core. By default, it is top_tb.");
+  CommandOptionId top_module_opt =
+    shell_cmd.add_option("top_module", false,
+                         "specify the top-level module name to be used in the "
+                         "testbench. Please avoid reserved words, i.e., "
+                         "fpga_top or fpga_core. By default, it is top_tb.");
   shell_cmd.set_option_require_value(top_module_opt, openfpga::OPT_STRING);
 
   /* add an option '--dut_module'*/
@@ -315,10 +317,12 @@ ShellCommandId add_write_testbench_template_command_template(
 
   /* add command to the shell */
   ShellCommandId shell_cmd_id = shell.add_command(
-    shell_cmd, "generate a template of testbench for a pre-configured fpga fabric", hidden);
+    shell_cmd,
+    "generate a template of testbench for a pre-configured fpga fabric",
+    hidden);
   shell.set_command_class(shell_cmd_id, cmd_class_id);
-  shell.set_command_execute_function(
-    shell_cmd_id, write_testbench_template_template<T>);
+  shell.set_command_execute_function(shell_cmd_id,
+                                     write_testbench_template_template<T>);
 
   /* add command dependency to the shell */
   shell.set_command_dependency(shell_cmd_id, dependent_cmds);
@@ -371,11 +375,14 @@ ShellCommandId add_write_testbench_io_connection_command_template(
   shell_cmd.add_option("verbose", false, "enable verbose output");
 
   /* add command to the shell */
-  ShellCommandId shell_cmd_id = shell.add_command(
-    shell_cmd, "generate a file to describe the connection to I/Os of a pre-configured fpga fabric", hidden);
+  ShellCommandId shell_cmd_id =
+    shell.add_command(shell_cmd,
+                      "generate a file to describe the connection to I/Os of a "
+                      "pre-configured fpga fabric",
+                      hidden);
   shell.set_command_class(shell_cmd_id, cmd_class_id);
-  shell.set_command_execute_function(
-    shell_cmd_id, write_testbench_io_connection_template<T>);
+  shell.set_command_execute_function(shell_cmd_id,
+                                     write_testbench_io_connection_template<T>);
 
   /* add command dependency to the shell */
   shell.set_command_dependency(shell_cmd_id, dependent_cmds);

openfpga/src/base/openfpga_verilog_template.h

@@ -222,9 +222,8 @@ int write_preconfigured_fabric_wrapper_template(
  *FPGA-Verilog
  *******************************************************************/
 template <class T>
-int write_testbench_template_template(
-  const T& openfpga_ctx, const Command& cmd,
-  const CommandContext& cmd_context) {
+int write_testbench_template_template(const T& openfpga_ctx, const Command& cmd,
+                                      const CommandContext& cmd_context) {
   CommandOptionId opt_output_dir = cmd.option("file");
   CommandOptionId opt_top_module = cmd.option("top_module");
   CommandOptionId opt_dut_module = cmd.option("dut_module");
@@ -267,9 +266,9 @@ int write_testbench_template_template(
  *FPGA-Verilog
  *******************************************************************/
 template <class T>
-int write_testbench_io_connection_template(
-  const T& openfpga_ctx, const Command& cmd,
-  const CommandContext& cmd_context) {
+int write_testbench_io_connection_template(const T& openfpga_ctx,
+                                           const Command& cmd,
+                                           const CommandContext& cmd_context) {
   CommandOptionId opt_output_dir = cmd.option("file");
   CommandOptionId opt_dut_module = cmd.option("dut_module");
   CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
@@ -304,9 +303,8 @@ int write_testbench_io_connection_template(
   }
 
   return fpga_verilog_testbench_io_connection(
-    openfpga_ctx.module_graph(),
-    g_vpr_ctx.atom(), g_vpr_ctx.placement(), pin_constraints, bus_group,
-    openfpga_ctx.io_location_map(), 
+    openfpga_ctx.module_graph(), g_vpr_ctx.atom(), g_vpr_ctx.placement(),
+    pin_constraints, bus_group, openfpga_ctx.io_location_map(),
     openfpga_ctx.module_name_map(), openfpga_ctx.fabric_global_port_info(),
     openfpga_ctx.vpr_netlist_annotation(), options);
 }

openfpga/src/fpga_verilog/verilog_api.cpp

@@ -20,11 +20,11 @@
 #include "verilog_grid.h"
 #include "verilog_mock_fpga_wrapper.h"
 #include "verilog_preconfig_top_module.h"
-#include "verilog_template_testbench.h"
-#include "verilog_testbench_io_connection.h"
 #include "verilog_routing.h"
 #include "verilog_simulation_info_writer.h"
 #include "verilog_submodule.h"
+#include "verilog_template_testbench.h"
+#include "verilog_testbench_io_connection.h"
 #include "verilog_tile.h"
 #include "verilog_top_module.h"
 #include "verilog_top_testbench.h"
@@ -264,14 +264,15 @@ int fpga_verilog_preconfigured_fabric_wrapper(
  *  - A wrapper module, which encapsulate the FPGA module in a Verilog module
  *which have the same port as the input benchmark
  ********************************************************************/
-int fpga_verilog_template_testbench(
-  const ModuleManager &module_manager,
-  const IoNameMap &io_name_map, const ModuleNameMap &module_name_map,
-  const VerilogTestbenchOption &options) {
+int fpga_verilog_template_testbench(const ModuleManager &module_manager,
+                                    const IoNameMap &io_name_map,
+                                    const ModuleNameMap &module_name_map,
+                                    const VerilogTestbenchOption &options) {
   vtr::ScopedStartFinishTimer timer(
     "Write a template testbench for a preconfigured FPGA fabric\n");
 
-  std::string src_dir_path = format_dir_path(find_path_dir_name(options.output_directory()));
+  std::string src_dir_path =
+    format_dir_path(find_path_dir_name(options.output_directory()));
   std::string testbench_file_path = options.output_directory();
 
   int status = CMD_EXEC_SUCCESS;
@@ -282,18 +283,17 @@ int fpga_verilog_template_testbench(
   /* Generate wrapper module for FPGA fabric (mapped by the input benchmark and
    * pre-configured testbench for verification */
   status = print_verilog_template_testbench(
-    module_manager, io_name_map, module_name_map, 
-    testbench_file_path, options);
+    module_manager, io_name_map, module_name_map, testbench_file_path, options);
 
   return status;
 }
 
 /********************************************************************
- * A top-level function of FPGA-Verilog which focuses on generating I/O connection part of testbenches
+ * A top-level function of FPGA-Verilog which focuses on generating I/O
+ *connection part of testbenches
  ********************************************************************/
 int fpga_verilog_testbench_io_connection(
-  const ModuleManager &module_manager,
-  const AtomContext &atom_ctx,
+  const ModuleManager &module_manager, const AtomContext &atom_ctx,
   const PlacementContext &place_ctx, const PinConstraints &pin_constraints,
   const BusGroup &bus_group, const IoLocationMap &io_location_map,
   const ModuleNameMap &module_name_map,
@@ -303,7 +303,8 @@ int fpga_verilog_testbench_io_connection(
   vtr::ScopedStartFinishTimer timer(
     "Write a template testbench for a preconfigured FPGA fabric\n");
 
-  std::string src_dir_path = format_dir_path(find_path_dir_name(options.output_directory()));
+  std::string src_dir_path =
+    format_dir_path(find_path_dir_name(options.output_directory()));
   std::string testbench_file_path = options.output_directory();
 
   std::string netlist_name = atom_ctx.nlist.netlist_name();
@@ -316,15 +317,13 @@ int fpga_verilog_testbench_io_connection(
   /* Generate wrapper module for FPGA fabric (mapped by the input benchmark and
    * pre-configured testbench for verification */
   status = print_verilog_testbench_io_connection(
-    module_manager, 
-    fabric_global_port_info, atom_ctx, place_ctx, pin_constraints, bus_group,
-    io_location_map, module_name_map, netlist_annotation,
-    netlist_name, testbench_file_path, options);
+    module_manager, fabric_global_port_info, atom_ctx, place_ctx,
+    pin_constraints, bus_group, io_location_map, module_name_map,
+    netlist_annotation, netlist_name, testbench_file_path, options);
 
   return status;
 }
 
-
 /********************************************************************
  * A top-level function of FPGA-Verilog which focuses on a wrapper module,
  * which encapsulate the application HDL into a mock FPGA module

openfpga/src/fpga_verilog/verilog_api.h

@@ -74,21 +74,19 @@ int fpga_verilog_preconfigured_fabric_wrapper(
   const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol,
   const VerilogTestbenchOption& options);
 
-int fpga_verilog_template_testbench(
-  const ModuleManager &module_manager,
-  const IoNameMap &io_name_map, const ModuleNameMap &module_name_map,
-  const VerilogTestbenchOption &options);
+int fpga_verilog_template_testbench(const ModuleManager& module_manager,
+                                    const IoNameMap& io_name_map,
+                                    const ModuleNameMap& module_name_map,
+                                    const VerilogTestbenchOption& options);
 
 int fpga_verilog_testbench_io_connection(
-  const ModuleManager &module_manager,
-  const AtomContext &atom_ctx,
-  const PlacementContext &place_ctx, const PinConstraints &pin_constraints,
-  const BusGroup &bus_group, const IoLocationMap &io_location_map,
-  const ModuleNameMap &module_name_map,
-  const FabricGlobalPortInfo &fabric_global_port_info,
-  const VprNetlistAnnotation &netlist_annotation,
-  const VerilogTestbenchOption &options);
-
+  const ModuleManager& module_manager, const AtomContext& atom_ctx,
+  const PlacementContext& place_ctx, const PinConstraints& pin_constraints,
+  const BusGroup& bus_group, const IoLocationMap& io_location_map,
+  const ModuleNameMap& module_name_map,
+  const FabricGlobalPortInfo& fabric_global_port_info,
+  const VprNetlistAnnotation& netlist_annotation,
+  const VerilogTestbenchOption& options);
 
 int fpga_verilog_mock_fpga_wrapper(
   const ModuleManager& module_manager, const AtomContext& atom_ctx,

openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp

@@ -18,8 +18,8 @@
 #include "openfpga_port.h"
 #include "openfpga_reserved_words.h"
 #include "verilog_constants.h"
-#include "verilog_preconfig_top_module_utils.h"
 #include "verilog_preconfig_top_module.h"
+#include "verilog_preconfig_top_module_utils.h"
 #include "verilog_testbench_utils.h"
 #include "verilog_writer_utils.h"
 
@@ -427,8 +427,9 @@ int print_verilog_preconfig_top_module(
   }
 
   /* Print internal wires */
-  print_verilog_preconfig_top_module_internal_wires(fp, module_manager,
-                                                    core_module, std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX));
+  print_verilog_preconfig_top_module_internal_wires(
+    fp, module_manager, core_module,
+    std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX));
 
   /* Instanciate FPGA top-level module */
   print_verilog_testbench_fpga_instance(
@@ -445,7 +446,8 @@ int print_verilog_preconfig_top_module(
    * signals! */
   status = print_verilog_preconfig_top_module_connect_global_ports(
     fp, module_manager, core_module, pin_constraints, global_ports,
-    benchmark_clock_port_names, std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX));
+    benchmark_clock_port_names,
+    std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX));
   if (CMD_EXEC_FATAL_ERROR == status) {
     return status;
   }

openfpga/src/fpga_verilog/verilog_preconfig_top_module.h

@@ -28,7 +28,6 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-
 int print_verilog_preconfig_top_module(
   const ModuleManager& module_manager,
   const BitstreamManager& bitstream_manager,
@@ -41,7 +40,6 @@ int print_verilog_preconfig_top_module(
   const std::string& circuit_name, const std::string& verilog_fname,
   const VerilogTestbenchOption& options);
 
-
 } /* end namespace openfpga */
 
 #endif

openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp

@@ -28,7 +28,7 @@ namespace openfpga {
  *******************************************************************/
 void print_verilog_preconfig_top_module_internal_wires(
   std::fstream &fp, const ModuleManager &module_manager,
-  const ModuleId &top_module, const std::string& port_postfix) {
+  const ModuleId &top_module, const std::string &port_postfix) {
   /* Validate the file stream */
   valid_file_stream(fp);
 
@@ -41,8 +41,7 @@ void print_verilog_preconfig_top_module_internal_wires(
       module_manager.module_port(top_module, module_port_id);
     /* Add a postfix to the internal wires to be different from other reserved
      * ports */
-    module_port.set_name(
-      module_port.get_name() + port_postfix);
+    module_port.set_name(module_port.get_name() + port_postfix);
     fp << generate_verilog_port(VERILOG_PORT_WIRE, module_port) << ";"
        << std::endl;
   }
@@ -60,7 +59,7 @@ int print_verilog_preconfig_top_module_connect_global_ports(
   const ModuleId &top_module, const PinConstraints &pin_constraints,
   const FabricGlobalPortInfo &fabric_global_ports,
   const std::vector<std::string> &benchmark_clock_port_names,
-  const std::string& port_postfix) {
+  const std::string &port_postfix) {
   /* Validate the file stream */
   valid_file_stream(fp);
 
@@ -84,10 +83,9 @@ int print_verilog_preconfig_top_module_connect_global_ports(
        */
       for (size_t pin_id = 0; pin_id < module_global_port.pins().size();
            ++pin_id) {
-        BasicPort module_clock_pin(
-          module_global_port.get_name() +
-            port_postfix,
-          module_global_port.pins()[pin_id], module_global_port.pins()[pin_id]);
+        BasicPort module_clock_pin(module_global_port.get_name() + port_postfix,
+                                   module_global_port.pins()[pin_id],
+                                   module_global_port.pins()[pin_id]);
 
         /* If the clock port name is in the pin constraints, we should wire it
          * to the constrained pin */
@@ -144,9 +142,7 @@ int print_verilog_preconfig_top_module_connect_global_ports(
       std::string constrained_net_name =
         pin_constraints.pin_net(module_global_pin);
 
-      module_global_pin.set_name(
-        module_global_port.get_name() +
-        port_postfix);
+      module_global_pin.set_name(module_global_port.get_name() + port_postfix);
 
       /* - If constrained to a given net in the benchmark, we connect the global
        * pin to the net

openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.h

@@ -30,14 +30,14 @@ namespace openfpga {
 
 void print_verilog_preconfig_top_module_internal_wires(
   std::fstream &fp, const ModuleManager &module_manager,
-  const ModuleId &top_module, const std::string& port_postfix);
+  const ModuleId &top_module, const std::string &port_postfix);
 
 int print_verilog_preconfig_top_module_connect_global_ports(
   std::fstream &fp, const ModuleManager &module_manager,
   const ModuleId &top_module, const PinConstraints &pin_constraints,
   const FabricGlobalPortInfo &fabric_global_ports,
-  const std::vector<std::string> &benchmark_clock_port_names, const std::string& port_postfix);
-
+  const std::vector<std::string> &benchmark_clock_port_names,
+  const std::string &port_postfix);
 
 } /* end namespace openfpga */
 

openfpga/src/fpga_verilog/verilog_template_testbench.cpp

@@ -18,8 +18,8 @@
 #include "openfpga_port.h"
 #include "openfpga_reserved_words.h"
 #include "verilog_constants.h"
-#include "verilog_template_testbench.h"
 #include "verilog_preconfig_top_module_utils.h"
+#include "verilog_template_testbench.h"
 #include "verilog_testbench_utils.h"
 #include "verilog_writer_utils.h"
 
@@ -29,7 +29,7 @@ namespace openfpga {
 /********************************************************************
  * Top-level function to generate a template testbench for a FPGA fabric.
  *
- *   Testbench 
+ *   Testbench
  *   +--------------------------------------------
  *   |
  *   |          FPGA fabric
@@ -50,14 +50,14 @@ namespace openfpga {
  *   |
  *   +-------------------------------------------
  *******************************************************************/
-int print_verilog_template_testbench(
-  const ModuleManager &module_manager,
-  const IoNameMap &io_name_map, const ModuleNameMap &module_name_map,
-  const std::string &verilog_fname,
-  const VerilogTestbenchOption &options) {
-  std::string timer_message =
-    std::string(
-      "Write a template Verilog testbench for pre-configured FPGA top-level netlist");
+int print_verilog_template_testbench(const ModuleManager &module_manager,
+                                     const IoNameMap &io_name_map,
+                                     const ModuleNameMap &module_name_map,
+                                     const std::string &verilog_fname,
+                                     const VerilogTestbenchOption &options) {
+  std::string timer_message = std::string(
+    "Write a template Verilog testbench for pre-configured FPGA top-level "
+    "netlist");
 
   int status = CMD_EXEC_SUCCESS;
 
@@ -76,7 +76,9 @@ int print_verilog_template_testbench(
     std::string("A template Verilog testbench for pre-configured FPGA fabric");
   print_verilog_file_header(fp, title, options.time_stamp());
 
-  print_verilog_comment(fp, std::string("Require an adaption to your needs before used for design verification!!!"));
+  print_verilog_comment(fp,
+                        std::string("Require an adaption to your needs before "
+                                    "used for design verification!!!"));
 
   print_verilog_default_net_type_declaration(fp, options.default_net_type());
 
@@ -118,10 +120,8 @@ int print_verilog_template_testbench(
     options.explicit_port_mapping());
 
   /* Testbench ends*/
-  print_verilog_module_end(
-    fp,
-    options.top_module(),
-    options.default_net_type());
+  print_verilog_module_end(fp, options.top_module(),
+                           options.default_net_type());
 
   /* Close the file stream */
   fp.close();