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[core] code format
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tangxifan committed Nov 26, 2024
1 parent 5a67d5d commit 6e89943
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Showing 7 changed files with 69 additions and 45 deletions.
24 changes: 16 additions & 8 deletions libs/libarchopenfpga/src/bitstream_setting.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -88,33 +88,39 @@ size_t BitstreamSetting::bitstream_offset(

std::string BitstreamSetting::default_mode_pb_type_name(
const BitstreamDefaultModeSettingId& default_mode_setting_id) const {
VTR_ASSERT(true == valid_bitstream_default_mode_setting_id(default_mode_setting_id));
VTR_ASSERT(true ==
valid_bitstream_default_mode_setting_id(default_mode_setting_id));
return default_mode_pb_type_names_[default_mode_setting_id];
}

std::vector<std::string> BitstreamSetting::default_mode_parent_pb_type_names(
const BitstreamDefaultModeSettingId& default_mode_setting_id) const {
VTR_ASSERT(true == valid_bitstream_default_mode_setting_id(default_mode_setting_id));
VTR_ASSERT(true ==
valid_bitstream_default_mode_setting_id(default_mode_setting_id));
return default_mode_parent_pb_type_names_[default_mode_setting_id];
}

std::vector<std::string> BitstreamSetting::default_mode_parent_mode_names(
const BitstreamDefaultModeSettingId& default_mode_setting_id) const {
VTR_ASSERT(true == valid_bitstream_default_mode_setting_id(default_mode_setting_id));
VTR_ASSERT(true ==
valid_bitstream_default_mode_setting_id(default_mode_setting_id));
return default_mode_parent_mode_names_[default_mode_setting_id];
}

std::vector<size_t> BitstreamSetting::default_mode_bits(
const BitstreamDefaultModeSettingId& default_mode_setting_id) const {
VTR_ASSERT(true == valid_bitstream_default_mode_setting_id(default_mode_setting_id));
VTR_ASSERT(true ==
valid_bitstream_default_mode_setting_id(default_mode_setting_id));
return pb_type_default_mode_bits_[default_mode_setting_id];
}

std::string BitstreamSetting::default_mode_bits_to_string(
const BitstreamDefaultModeSettingId& default_mode_setting_id) const {
VTR_ASSERT(true == valid_bitstream_default_mode_setting_id(default_mode_setting_id));
VTR_ASSERT(true ==
valid_bitstream_default_mode_setting_id(default_mode_setting_id));
std::string mode_bits_str;
for (const size_t& bit : pb_type_default_mode_bits_[default_mode_setting_id]) {
for (const size_t& bit :
pb_type_default_mode_bits_[default_mode_setting_id]) {
mode_bits_str += std::to_string(bit);
}
return mode_bits_str;
Expand Down Expand Up @@ -199,7 +205,8 @@ void BitstreamSetting::set_bitstream_offset(
bitstream_offsets_[pb_type_setting_id] = offset;
}

BitstreamDefaultModeSettingId BitstreamSetting::add_bitstream_default_mode_setting(
BitstreamDefaultModeSettingId
BitstreamSetting::add_bitstream_default_mode_setting(
const std::string& pb_type_name,
const std::vector<std::string>& parent_pb_type_names,
const std::vector<std::string>& parent_mode_names,
Expand Down Expand Up @@ -279,7 +286,8 @@ bool BitstreamSetting::valid_bitstream_pb_type_setting_id(
bool BitstreamSetting::valid_bitstream_default_mode_setting_id(
const BitstreamDefaultModeSettingId& default_mode_setting_id) const {
return (size_t(default_mode_setting_id) < default_mode_setting_ids_.size()) &&
(default_mode_setting_id == default_mode_setting_ids_[default_mode_setting_id]);
(default_mode_setting_id ==
default_mode_setting_ids_[default_mode_setting_id]);
}

bool BitstreamSetting::valid_bitstream_interconnect_setting_id(
Expand Down
8 changes: 5 additions & 3 deletions libs/libarchopenfpga/src/bitstream_setting.h
Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,8 @@
#include <vector>

#include "bitstream_setting_fwd.h"
#include "vtr_vector.h"
#include "vtr_geometry.h"
#include "vtr_vector.h"

/* namespace openfpga begins */
namespace openfpga {
Expand Down Expand Up @@ -189,12 +189,14 @@ class BitstreamSetting {
/* Pb type - default mode bits overwrite */
vtr::vector<BitstreamDefaultModeSettingId, BitstreamDefaultModeSettingId>
default_mode_setting_ids_;
vtr::vector<BitstreamDefaultModeSettingId, std::string> default_mode_pb_type_names_;
vtr::vector<BitstreamDefaultModeSettingId, std::string>
default_mode_pb_type_names_;
vtr::vector<BitstreamDefaultModeSettingId, std::vector<std::string>>
default_mode_parent_pb_type_names_;
vtr::vector<BitstreamDefaultModeSettingId, std::vector<std::string>>
default_mode_parent_mode_names_;
vtr::vector<BitstreamDefaultModeSettingId, std::vector<size_t>> pb_type_default_mode_bits_;
vtr::vector<BitstreamDefaultModeSettingId, std::vector<size_t>>
pb_type_default_mode_bits_;

/* Interconnect-related settings:
* - Name of interconnect under a given pb_type
Expand Down
11 changes: 7 additions & 4 deletions libs/libarchopenfpga/src/read_xml_bitstream_setting.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,8 @@ static void read_xml_bitstream_pb_type_setting(
}

/********************************************************************
* Parse XML description for a pb_type annotation under a <default_mode_bits> XML node
* Parse XML description for a pb_type annotation under a <default_mode_bits>
*XML node
*******************************************************************/
static void read_xml_bitstream_default_mode_setting(
pugi::xml_node& xml_pb_type, const pugiutil::loc_data& loc_data,
Expand All @@ -70,7 +71,8 @@ static void read_xml_bitstream_default_mode_setting(

const std::string& mode_bits_attr =
get_attribute(xml_pb_type, "mode_bits", loc_data).as_string();
std::vector<size_t> mode_bits = parse_mode_bits(xml_pb_type, loc_data, mode_bits_attr);
std::vector<size_t> mode_bits =
parse_mode_bits(xml_pb_type, loc_data, mode_bits_attr);

/* Add to bitstream setting */
bitstream_setting.add_bitstream_default_mode_setting(
Expand Down Expand Up @@ -159,7 +161,7 @@ openfpga::BitstreamSetting read_xml_bitstream_setting(
* each child should be named after <pb_type>
*/
for (pugi::xml_node xml_child : Node.children()) {
/* Error out if the XML child has an invalid name!
/* Error out if the XML child has an invalid name!
* TODO: Use std::map or something similar to apply checks!
*/
if ((xml_child.name() != std::string("pb_type")) &&
Expand All @@ -168,7 +170,8 @@ openfpga::BitstreamSetting read_xml_bitstream_setting(
(xml_child.name() != std::string("non_fabric")) &&
(xml_child.name() != std::string("overwrite_bitstream"))) {
bad_tag(xml_child, loc_data, Node,
{"pb_type | interconnect | default_mode_bits | non_fabric | overwrite_bitstream"});
{"pb_type | interconnect | default_mode_bits | non_fabric | "
"overwrite_bitstream"});
}

if (xml_child.name() == std::string("pb_type")) {
Expand Down
28 changes: 16 additions & 12 deletions libs/libarchopenfpga/src/write_xml_bitstream_setting.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -55,32 +55,35 @@ static std::string generate_bitstream_setting_pb_type_hierarchy_name(
const BitstreamDefaultModeSettingId& bitstream_pb_type_setting_id) {
/* Iterate over the parent_pb_type and modes names, they should well match */
VTR_ASSERT_SAFE(
bitstream_setting.default_mode_parent_pb_type_names(bitstream_pb_type_setting_id)
.size() ==
bitstream_setting.default_mode_parent_mode_names(bitstream_pb_type_setting_id).size());
bitstream_setting
.default_mode_parent_pb_type_names(bitstream_pb_type_setting_id)
.size() == bitstream_setting
.default_mode_parent_mode_names(bitstream_pb_type_setting_id)
.size());

std::string hie_name;

for (size_t i = 0;
i < bitstream_setting.default_mode_parent_pb_type_names(bitstream_pb_type_setting_id)
i < bitstream_setting
.default_mode_parent_pb_type_names(bitstream_pb_type_setting_id)
.size();
++i) {
hie_name +=
bitstream_setting.default_mode_parent_pb_type_names(bitstream_pb_type_setting_id)[i];
hie_name += bitstream_setting.default_mode_parent_pb_type_names(
bitstream_pb_type_setting_id)[i];
hie_name += std::string("[");
hie_name +=
bitstream_setting.default_mode_parent_mode_names(bitstream_pb_type_setting_id)[i];
hie_name += bitstream_setting.default_mode_parent_mode_names(
bitstream_pb_type_setting_id)[i];
hie_name += std::string("]");
hie_name += std::string(".");
}

/* Add the leaf pb_type */
hie_name += bitstream_setting.default_mode_pb_type_name(bitstream_pb_type_setting_id);
hie_name +=
bitstream_setting.default_mode_pb_type_name(bitstream_pb_type_setting_id);

return hie_name;
}


/********************************************************************
* Generate the full hierarchy name for an interconnect in bitstream setting
*******************************************************************/
Expand Down Expand Up @@ -173,7 +176,8 @@ static void write_xml_bitstream_default_mode_setting(

write_xml_attribute(
fp, "mode_bits",
bitstream_setting.default_mode_bits_to_string(bitstream_default_mode_setting_id)
bitstream_setting
.default_mode_bits_to_string(bitstream_default_mode_setting_id)
.c_str());
fp << "/>"
<< "\n";
Expand Down Expand Up @@ -231,7 +235,7 @@ void write_xml_bitstream_setting(
for (const auto& bitstream_default_mode_setting_id :
bitstream_setting.default_mode_settings()) {
write_xml_bitstream_default_mode_setting(fp, fname, bitstream_setting,
bitstream_default_mode_setting_id);
bitstream_default_mode_setting_id);
}

/* Write interconnect -related settings */
Expand Down
37 changes: 22 additions & 15 deletions openfpga/src/annotation/annotate_bitstream_setting.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -142,14 +142,15 @@ static int annotate_bitstream_default_mode_setting(
std::vector<std::string> target_pb_type_names;
std::vector<std::string> target_pb_mode_names;

target_pb_type_names =
bitstream_setting.default_mode_parent_pb_type_names(bitstream_default_mode_setting_id);
target_pb_type_names.push_back(
bitstream_setting.default_mode_pb_type_name(bitstream_default_mode_setting_id));
target_pb_mode_names =
bitstream_setting.default_mode_parent_mode_names(bitstream_default_mode_setting_id);
target_pb_type_names = bitstream_setting.default_mode_parent_pb_type_names(
bitstream_default_mode_setting_id);
target_pb_type_names.push_back(bitstream_setting.default_mode_pb_type_name(
bitstream_default_mode_setting_id));
target_pb_mode_names = bitstream_setting.default_mode_parent_mode_names(
bitstream_default_mode_setting_id);

std::vector<size_t> mode_bits = bitstream_setting.default_mode_bits(bitstream_default_mode_setting_id);
std::vector<size_t> mode_bits =
bitstream_setting.default_mode_bits(bitstream_default_mode_setting_id);

/* Pb type information are located at the logic_block_types in the device
* context of VPR We iterate over the vectors and find the pb_type matches
Expand Down Expand Up @@ -177,16 +178,22 @@ static int annotate_bitstream_default_mode_setting(
}

/* Found one, pre-check and build annotation */
if (vpr_device_annotation.pb_type_mode_bits(target_pb_type).size() != mode_bits.size()) {
if (vpr_device_annotation.pb_type_mode_bits(target_pb_type).size() !=
mode_bits.size()) {
VTR_LOG_ERROR(
"Mismatches in length of default mode bits for a pb_type '%s' which is defined in bitstream setting ('%s') "
"Mismatches in length of default mode bits for a pb_type '%s' which "
"is defined in bitstream setting ('%s') "
"from OpenFPGA architecture description ('%s')\n",
target_pb_type_names[0].c_str(), bitstream_setting.default_mode_bits_to_string(bitstream_default_mode_setting_id).c_str(),
vpr_device_annotation.pb_type_mode_bits_to_string(target_pb_type).c_str());
target_pb_type_names[0].c_str(),
bitstream_setting
.default_mode_bits_to_string(bitstream_default_mode_setting_id)
.c_str(),
vpr_device_annotation.pb_type_mode_bits_to_string(target_pb_type)
.c_str());
return CMD_EXEC_FATAL_ERROR;
}
vpr_device_annotation.add_pb_type_mode_bits(
target_pb_type, mode_bits, false);
vpr_device_annotation.add_pb_type_mode_bits(target_pb_type, mode_bits,
false);
link_success = true;
}

Expand Down Expand Up @@ -345,8 +352,8 @@ int annotate_bitstream_setting(
return status;
}

status = annotate_bitstream_default_mode_setting(bitstream_setting, vpr_device_ctx,
vpr_device_annotation);
status = annotate_bitstream_default_mode_setting(
bitstream_setting, vpr_device_ctx, vpr_device_annotation);
if (status == CMD_EXEC_FATAL_ERROR) {
return status;
}
Expand Down
4 changes: 2 additions & 2 deletions openfpga/src/annotation/annotate_pb_types.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -990,8 +990,8 @@ static bool link_primitive_pb_type_to_mode_bits(
}

/* Update the annotation */
vpr_device_annotation.add_pb_type_mode_bits(primitive_pb_type,
pb_type_annotation.mode_bits(), true);
vpr_device_annotation.add_pb_type_mode_bits(
primitive_pb_type, pb_type_annotation.mode_bits(), true);

return true;
}
Expand Down
2 changes: 1 addition & 1 deletion openfpga/src/annotation/vpr_device_annotation.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -575,7 +575,7 @@ void VprDeviceAnnotation::add_pb_type_mode_bits(
pb_type_mode_bits_.find(pb_type);
if (it != pb_type_mode_bits_.end()) {
VTR_LOGV_WARN(verbose, "Override the mode bits mapping for pb_type '%s'!\n",
pb_type->name);
pb_type->name);
}

pb_type_mode_bits_[pb_type] = mode_bits;
Expand Down

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