Merge pull request #1794 from lnis-uofu/xt_pbfixup

support global net fixup in pb pin fixup

openfpga/src/base/openfpga_pb_pin_fixup.h

@@ -14,7 +14,7 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void update_pb_pin_with_post_routing_results(
+int update_pb_pin_with_post_routing_results(
   const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx,
   const PlacementContext& placement_ctx,
   const VprRoutingAnnotation& vpr_routing_annotation,

openfpga/src/base/openfpga_pb_pin_fixup_template.h

@@ -38,15 +38,12 @@ int pb_pin_fixup_template(T& openfpga_context, const Command& cmd,
   CommandOptionId opt_verbose = cmd.option("verbose");
 
   /* Apply fix-up to each grid */
-  update_pb_pin_with_post_routing_results(
+  return update_pb_pin_with_post_routing_results(
     g_vpr_ctx.device(), g_vpr_ctx.clustering(), g_vpr_ctx.placement(),
     openfpga_context.vpr_routing_annotation(),
     openfpga_context.mutable_vpr_clustering_annotation(),
     g_vpr_ctx.device().arch->perimeter_cb,
     cmd_context.option_enable(cmd, opt_verbose));
-
-  /* TODO: should identify the error code from internal function execution */
-  return CMD_EXEC_SUCCESS;
 }
 
 } /* end namespace openfpga */

openfpga/src/fpga_bitstream/build_routing_bitstream.cpp

@@ -380,7 +380,8 @@ static void build_connection_block_interc_bitstream(
   const bool& verbose) {
   RRNodeId src_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, ipin_index);
 
-  VTR_LOGV(verbose, "\tGenerating bitstream for IPIN '%lu'\n", ipin_index);
+  VTR_LOGV(verbose, "\tGenerating bitstream for IPIN '%lu'. Details: %s\n",
+           ipin_index, rr_graph.node_coordinate_to_string(src_rr_node).c_str());
 
   /* Consider configurable edges only */
   std::vector<RREdgeId> driver_rr_edges =

openfpga_flow/openfpga_shell_scripts/example_clkntwk_pb_pin_fixup_no_ace_script.openfpga

@@ -0,0 +1,78 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} \
+  --clock_modeling ideal \
+  --device ${OPENFPGA_VPR_DEVICE_LAYOUT} \
+  --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} \
+  --skip_sync_clustering_and_routing_results on
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Read OpenFPGA clock architecture
+read_openfpga_clock_arch -f ${OPENFPGA_CLOCK_ARCH_FILE}
+
+# Append clock network to vpr's routing resource graph
+append_clock_rr_graph
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --sort_gsb_chan_node_in_edges
+
+pb_pin_fixup --verbose
+
+# Route clock based on clock network definition
+route_clock_rr_graph ${OPENFPGA_ROUTE_CLOCK_OPTIONS} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing #--verbose
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack --design_constraints ${OPENFPGA_REPACK_CONSTRAINTS_FILE} #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_PORT_MAPPING} --include_signal_init --bitstream fabric_bitstream.bit  --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} 
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_PORT_MAPPING} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} 
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_PORT_MAPPING} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} 
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory

openfpga_flow/regression_test_scripts/basic_reg_test.sh

@@ -247,6 +247,7 @@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer $@
 run-task basic_tests/clock_network/homo_1clock_1reset_3layer_2entry $@
 run-task basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry $@
 run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut $@
+run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup $@
 run-task basic_tests/clock_network/homo_1clock_1reset_2layer_syntax $@
 run-task basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines $@
 run-task basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver $@

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/clk_arch_1clk_1rst_2layer.xml

@@ -0,0 +1,34 @@
+<clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0"> 
+  <clock_network name="clk_tree_2lvl" global_port="op_clk[0:0]"> 
+    <spine name="clk_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1"> 
+      <switch_point tap="clk_rib_lvl1_sw0_upper" x="1" y="1"/> 
+      <switch_point tap="clk_rib_lvl1_sw0_lower" x="1" y="1"/> 
+      <switch_point tap="clk_rib_lvl1_sw1_upper" x="2" y="1"/> 
+      <switch_point tap="clk_rib_lvl1_sw1_lower" x="2" y="1"/> 
+    </spine>  
+    <spine name="clk_rib_lvl1_sw0_upper" start_x="1" start_y="2" end_x="1" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
+    <spine name="clk_rib_lvl1_sw0_lower" start_x="1" start_y="1" end_x="1" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
+    <spine name="clk_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
+    <spine name="clk_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
+    <taps>
+      <all from_pin="op_clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
+      <all from_pin="op_clk[0:0]" to_pin="clb[0:0].I[0:11]"/>
+    </taps>
+  </clock_network>  
+  <clock_network name="rst_tree_2lvl" global_port="op_reset[0:0]"> 
+    <spine name="rst_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1"> 
+      <switch_point tap="rst_rib_lvl1_sw0_upper" x="1" y="1"/> 
+      <switch_point tap="rst_rib_lvl1_sw0_lower" x="1" y="1"/> 
+      <switch_point tap="rst_rib_lvl1_sw1_upper" x="2" y="1"/> 
+      <switch_point tap="rst_rib_lvl1_sw1_lower" x="2" y="1"/> 
+    </spine>  
+    <spine name="rst_rib_lvl1_sw0_upper" start_x="1" start_y="2" end_x="1" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
+    <spine name="rst_rib_lvl1_sw0_lower" start_x="1" start_y="1" end_x="1" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
+    <spine name="rst_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
+    <spine name="rst_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
+    <taps>
+      <all from_pin="op_reset[0:0]" to_pin="clb[0:0].reset[0:0]"/>
+      <all from_pin="op_reset[0:0]" to_pin="clb[0:0].I[0:11]"/>
+    </taps>
+  </clock_network>  
+</clock_networks> 

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/pin_constraints_clk.xml

@@ -0,0 +1,8 @@
+<pin_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the reset signal to the op_reset[0] port of the FPGA fabric
+    -->
+  <set_io pin="op_reset[0]" net="OPEN"/>
+  <set_io pin="op_clk[0]" net="clk"/>
+</pin_constraints>
+

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/pin_constraints_rst.xml

@@ -0,0 +1,8 @@
+<pin_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the reset signal to the op_reset[0] port of the FPGA fabric
+    -->
+  <set_io pin="op_reset[0]" net="rst"/>
+  <set_io pin="op_clk[0]" net="clk"/>
+</pin_constraints>
+

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/pin_constraints_rst_and_clk.xml

@@ -0,0 +1,8 @@
+<pin_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the reset signal to the op_reset[0] port of the FPGA fabric
+    -->
+  <set_io pin="op_reset[0]" net="rst"/>
+  <set_io pin="op_clk[0]" net="clk"/>
+</pin_constraints>
+

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/repack_pin_constraints.xml

@@ -0,0 +1,4 @@
+<repack_design_constraints>
+  <!-- Intended to be dummy -->
+</repack_design_constraints>
+

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/task.conf

@@ -0,0 +1,56 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 3*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_pb_pin_fixup_no_ace_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml
+openfpga_vpr_device_layout=2x2
+openfpga_vpr_route_chan_width=32
+openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml
+openfpga_verilog_testbench_port_mapping=--explicit_port_mapping
+openfpga_route_clock_options=
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_on_lut/clk_on_lut.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v
+
+[SYNTHESIS_PARAM]
+# Yosys script parameters
+bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
+bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
+bench_read_verilog_options_common = -nolatches
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
+
+bench0_top = rst_on_lut
+bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst.xml
+
+bench1_top = clk_on_lut
+bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk.xml
+
+bench2_top = rst_and_clk_on_lut
+bench2_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_and_clk.xml
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=