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Merge pull request #1776 from lnis-uofu/xt_doc
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[doc] format to resolve latexpdf build errors; now local build passes
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tangxifan authored Aug 3, 2024
2 parents 328c387 + c11a2c7 commit a7920b1
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4 changes: 2 additions & 2 deletions docs/source/manual/file_formats/tile_config_file.rst
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Expand Up @@ -28,6 +28,8 @@ Detailed syntax are presented as follows.

The ``top_left`` is a shortcut to define the organization for all the tiles. :numref:`fig_tile_style_top_left` shows an example of tiles in the top-left sytle, where the programmable block locates in the top-left corner of all the tiles, surrounded by two connection blocks and one switch blocks.

The ``bottom_left`` is a shortcut to define the organization for all the tiles. :numref:`fig_tile_style_bottom_left` shows an example of tiles in the bottom-left sytle, where the programmable block locates in the bottom-left corner of all the tiles, surrounded by two connection blocks and one switch blocks.

.. _fig_tile_style_top_left:

.. figure:: ./figures/tile_style_top_left.png
Expand All @@ -37,8 +39,6 @@ Detailed syntax are presented as follows.
An example of top-left style of a tile in FPGA fabric


The ``bottom_left`` is a shortcut to define the organization for all the tiles. :numref:`fig_tile_style_bottom_left` shows an example of tiles in the bottom-left sytle, where the programmable block locates in the bottom-left corner of all the tiles, surrounded by two connection blocks and one switch blocks.

.. _fig_tile_style_bottom_left:

.. figure:: ./figures/tile_style_bottom_left.png
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