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Bump yosys from 0200a76 to 11e94cc
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Bumps [yosys](https://github.com/YosysHQ/yosys) from `0200a76` to `11e94cc`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](YosysHQ/yosys@0200a76...11e94cc)

---
updated-dependencies:
- dependency-name: yosys
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <[email protected]>
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@dependabot
dependabot[bot] authored Oct 16, 2024
1 parent fc0cf2e commit df01b2b
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion yosys
Submodule yosys updated 98 files
+3 −0 .gitmodules
+3 −3 Makefile
+1 −1 backends/blif/blif.cc
+3 −3 backends/btor/btor.cc
+7 −7 backends/cxxrtl/cxxrtl_backend.cc
+9 −3 backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h
+7 −7 backends/edif/edif.cc
+3 −3 backends/firrtl/firrtl.cc
+1 −1 backends/functional/test_generic.cc
+4 −4 backends/intersynth/intersynth.cc
+6 −6 backends/rtlil/rtlil_backend.cc
+1 −1 backends/simplec/simplec.cc
+6 −6 backends/smt2/smt2.cc
+12 −12 backends/verilog/verilog_backend.cc
+1 −1 frontends/aiger/aigerparse.cc
+12 −29 frontends/ast/ast.cc
+5 −5 frontends/ast/genrtlil.cc
+33 −33 frontends/ast/simplify.cc
+10 −10 frontends/blif/blifparse.cc
+1 −1 frontends/rtlil/rtlil_parser.y
+19 −37 frontends/verific/verific.cc
+1 −1 frontends/verific/verificsva.cc
+1 −0 frontends/verilog/verilog_parser.y
+1 −1 kernel/bitpattern.h
+85 −85 kernel/calc.cc
+8 −8 kernel/celltypes.h
+7 −7 kernel/consteval.h
+215 −323 kernel/driver.cc
+5 −5 kernel/drivertools.cc
+7 −7 kernel/ff.cc
+3 −3 kernel/ffinit.h
+12 −12 kernel/ffmerge.cc
+2 −1 kernel/functional.h
+2 −2 kernel/macc.h
+26 −26 kernel/mem.cc
+1 −1 kernel/mem.h
+282 −51 kernel/rtlil.cc
+118 −26 kernel/rtlil.h
+2 −2 kernel/satgen.cc
+3 −0 kernel/yosys_common.h
+2 −2 kernel/yw.cc
+1 −0 libs/cxxopts
+1 −1 passes/cmds/bugpoint.cc
+1 −1 passes/cmds/clean_zerowidth.cc
+1 −1 passes/cmds/dft_tag.cc
+2 −2 passes/cmds/printattrs.cc
+4 −4 passes/cmds/setundef.cc
+1 −1 passes/cmds/splitnets.cc
+6 −6 passes/cmds/xprop.cc
+2 −2 passes/fsm/fsm_extract.cc
+15 −15 passes/fsm/fsm_map.cc
+11 −11 passes/fsm/fsm_opt.cc
+3 −3 passes/fsm/fsm_recode.cc
+13 −13 passes/fsm/fsmdata.h
+2 −2 passes/hierarchy/hierarchy.cc
+4 −4 passes/hierarchy/submod.cc
+5 −5 passes/memory/memory_bram.cc
+5 −5 passes/memory/memory_libmap.cc
+2 −2 passes/memory/memory_share.cc
+4 −4 passes/opt/muxpack.cc
+5 −5 passes/opt/opt_clean.cc
+4 −4 passes/opt/opt_dff.cc
+8 −8 passes/opt/opt_expr.cc
+4 −4 passes/opt/opt_ffinv.cc
+1 −1 passes/opt/opt_lut.cc
+2 −2 passes/opt/opt_lut_ins.cc
+6 −6 passes/opt/opt_mem.cc
+6 −6 passes/opt/pmux2shiftx.cc
+11 −11 passes/opt/share.cc
+2 −2 passes/opt/wreduce.cc
+2 −2 passes/pmgen/microchip_dsp.cc
+5 −5 passes/pmgen/xilinx_dsp.cc
+1 −1 passes/pmgen/xilinx_dsp.pmg
+2 −2 passes/pmgen/xilinx_srl.cc
+3 −3 passes/proc/proc_init.cc
+1 −1 passes/proc/proc_memwr.cc
+8 −8 passes/proc/proc_rom.cc
+4 −4 passes/sat/eval.cc
+1 −1 passes/sat/expose.cc
+3 −3 passes/sat/formalff.cc
+8 −8 passes/sat/sat.cc
+17 −17 passes/sat/sim.cc
+3 −3 passes/techmap/abc9_ops.cc
+1 −1 passes/techmap/cellmatch.cc
+4 −4 passes/techmap/dffinit.cc
+4 −4 passes/techmap/dfflegalize.cc
+1 −1 passes/techmap/flowmap.cc
+2 −2 passes/techmap/techmap.cc
+3 −3 passes/techmap/zinit.cc
+2 −2 passes/tests/test_cell.cc
+2 −2 techlibs/gatemate/gatemate_foldinv.cc
+8 −8 techlibs/greenpak4/greenpak4_dffinv.cc
+3 −3 techlibs/microchip/microchip_dffopt.cc
+6 −4 techlibs/quicklogic/ql_dsp_simd.cc
+15 −1 techlibs/xilinx/synth_xilinx.cc
+4 −4 techlibs/xilinx/xilinx_dffopt.cc
+1 −1 tests/unit/Makefile
+71 −6 tests/unit/kernel/rtlilTest.cc

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