Now use relative index to name module ports of tile modules

[tangxifan]

Motivate of the pull request

• To address an existing issue. If so, please provide a link to the issue:
• Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

Currently, OpenFPGA has the following limitations:

• In the tile modules, the names of ports have to be unique. However, when the option --name_module_using_index is enabled, the port name includes a prefix of unique SB/CB modules, to indicate the source of the port (in the context of subblocks inside the tile). However, this may cause naming conflicts when there are multiple same SB/CB modules in the same tile.

What does this pull request change?

This PR improves in the following aspects:

• Now we use the relative index of CB/SB in each tile. For example, sb_1__1_ is the first SB in the tile module, it is named as sb_0_, while the sb_1__2_ is the second SB in the tile module, it is names as sb_1_

Which part of the code base require a change

• VPR
• Tileable routing architecture generator
• OpenFPGA libraries
• FPGA-Verilog
• FPGA-Bitstream
• FPGA-SDC
• FPGA-SPICE
• Flow scripts
• Architecture library
• Cell library
• Documentation
• Regression tests
• Continous Integration (CI) scripts

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.