Support testbench template generation and I/O connection generation

[tangxifan]

Motivate of the pull request

• To address an existing issue. If so, please provide a link to the issue: Option to write hierarchical preconfigured wrapper #1425
• Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

Currently, OpenFPGA has the following limitations:

• As stated in Option to write hierarchical preconfigured wrapper #1425

What does this pull request change?

This PR improves in the following aspects:

• a new command write_testbench_io_connection will be added with the following option
• a new command write_testbench_template will be added with the following option

Which part of the code base require a change

• VPR
• Tileable routing architecture generator
• OpenFPGA libraries
• FPGA-Verilog
• FPGA-Bitstream
• FPGA-SDC
• FPGA-SPICE
• Flow scripts
• Architecture library
• Cell library
• Documentation
• Regression tests
• Continous Integration (CI) scripts

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.