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Bump vtr-verilog-to-routing from 876311a to 6ce3706 #1876

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merged 1 commit into from
Oct 24, 2024
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Bump vtr-verilog-to-routing from 876311a to 6ce3706 #1876

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2 changes: 1 addition & 1 deletion vtr-verilog-to-routing
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Submodule vtr-verilog-to-routing updated 79 files
+5 −0 .gitignore
+7 −0 doc/src/api/vpr/route_tree.rst
+2 −19 doc/src/api/vprinternals/router_heap.rst
+10 −6 doc/src/vpr/command_line_usage.rst
+1 −1 libs/libarchfpga/src/physical_types.h
+1 −1 utils/route_diag/src/main.cpp
+2 −2 vpr/src/base/SetupVPR.cpp
+4 −7 vpr/src/base/ShowSetup.cpp
+1 −1 vpr/src/base/place_and_route.cpp
+8 −12 vpr/src/base/read_options.cpp
+1 −1 vpr/src/base/read_options.h
+1 −3 vpr/src/base/read_route.cpp
+6 −2 vpr/src/base/vpr_types.h
+71 −4 vpr/src/place/net_cost_handler.cpp
+19 −0 vpr/src/place/net_cost_handler.h
+0 −77 vpr/src/route/binary_heap.cpp
+0 −17 vpr/src/route/binary_heap.h
+0 −550 vpr/src/route/bucket.cpp
+0 −307 vpr/src/route/bucket.h
+212 −235 vpr/src/route/connection_router.cpp
+64 −43 vpr/src/route/connection_router.h
+8 −5 vpr/src/route/connection_router_interface.h
+74 −0 vpr/src/route/d_ary_heap.h
+162 −0 vpr/src/route/d_ary_heap.tpp
+0 −107 vpr/src/route/four_ary_heap.cpp
+0 −35 vpr/src/route/four_ary_heap.h
+1 −59 vpr/src/route/heap_type.cpp
+39 −192 vpr/src/route/heap_type.h
+0 −173 vpr/src/route/k_ary_heap.cpp
+0 −125 vpr/src/route/k_ary_heap.h
+0 −17 vpr/src/route/netlist_routers.h
+2 −2 vpr/src/route/route.cpp
+9 −7 vpr/src/route/route_common.cpp
+0 −95 vpr/src/route/route_common.h
+6 −6 vpr/src/route/route_net.tpp
+15 −16 vpr/src/route/route_path_manager.h
+6 −6 vpr/src/route/route_tree.cpp
+40 −2 vpr/src/route/route_tree.h
+1 −0 vpr/src/route/route_tree_fwd.h
+3 −6 vpr/src/route/route_utils.cpp
+3 −3 vpr/src/route/route_utils.h
+2 −2 vpr/src/route/router_delay_profiling.cpp
+0 −2 vpr/src/route/router_delay_profiling.h
+3 −3 vpr/src/route/router_stats.h
+1 −1 vpr/test/test_connection_router.cpp
+3,390 −0 vtr_flow/arch/xilinx/7series_BRAM_DSP_carry.xml
+1 −1 vtr_flow/benchmarks/titan_blif/README.rst
+505 −0 vtr_flow/benchmarks/titan_blif/utility_scripts/q2_flow.tcl
+ − vtr_flow/benchmarks/titan_blif/utility_scripts/titan_flow_with_hard_blocks_procedure.docx
+1 −0 vtr_flow/parse/parse_config/vpr_fixed_chan_width.txt
+1 −1 vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_route_fixed_chan_width.txt
+2 −2 vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_route_min_chan_width_small.txt
+19 −0 vtr_flow/parse/pass_requirements/pass_requirements_vpr_xilinx_fixed_width.txt
+3 −3 vtr_flow/parse/pass_requirements/timing/pass_requirements.vpr_route_relaxed_chan_width_small.txt
+12 −0 vtr_flow/parse/qor_config/qor_vpr_xilinx.txt
+96 −1 vtr_flow/scripts/python_libs/vtr/task.py
+1 −1 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/config.txt
+1 −1 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
+31 −31 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt
+15 −15 ...low/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt
+34 −0 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/config.txt
+7 −0 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/golden_results.txt
+1 −1 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/vtr_reg_qor_large_depop_run_flat/config/config.txt
+0 −28 vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/ch_intrinsics/config/config.txt
+52 −0 vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/config.txt
+5 −0 vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt
+0 −0 vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/constraints/ch_intrinsics_fixed_io.xml
+0 −0 vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/constraints/diffeq1_fixed_io.xml
+0 −0 vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/constraints/single_ff_fixed_io.xml
+0 −0 vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/constraints/single_wire_fixed_io.xml
+0 −28 vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/diffeq1/config/config.txt
+0 −28 vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/single_ff/config/config.txt
+0 −2 vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/single_ff/config/golden_results.txt
+0 −28 vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/single_wire/config/config.txt
+0 −2 vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/single_wire/config/golden_results.txt
+0 −5 vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/task_list.txt
+5 −5 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt
+3 −3 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt
+1 −4 vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt
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