Timing annotation

[apond308]

Motivate of the pull request

• To address an existing issue. If so, please provide a link to the issue:
• Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

Currently, the architecture timing values are hardcoded into the arch files.

What does this pull request change?

It adds timing annotation files so that the timing values are read into variables in the arch files.

Which part of the code base require a change

• VPR
• Tileable routing architecture generator
• OpenFPGA libraries
• FPGA-Verilog
• FPGA-Bitstream
• FPGA-SDC
• FPGA-SPICE
• Flow scripts
• Architecture library
• Cell library
• Documentation
• Regression tests
• Continous Integration (CI) scripts

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.

[tangxifan]

@apond308 Some comments on the details. This PR is on the right track. Just need some effort to make it clean.

Since you have added a few benchmarks and new architectures, can you add new test cases?

[tangxifan]

Depending on the test, you want to run, you may not need a new script.
If you just want to test bitstream generation, you can reuse this script: https://github.com/lnis-uofu/OpenFPGA/blob/master/openfpga_flow/openfpga_shell_scripts/generate_bitstream_global_tile_multiclock_example_script.openfpga

On the other side, the VexRiscV and picorv benchmarks are too big to be tested on CI (iVerilog may takes hours to finish). I suggest just testing bitstream on CI.

Also to avoid adding new script, you may also consider to add options to the script which can be customized in task configuration file.
For example,

OpenFPGA/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga

Line 3 in 223e06d

vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT}

You can define the variable ${OPENFPGA_<your_own_variable_name>}

In task configuration file, you can define the content of the variable:

OpenFPGA/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/config/task.conf

Line 22 in 223e06d

openfpga_vpr_device_layout=

[apond308]

I see what you're saying about avoiding adding a new script, but how would you disable the '--clock_modeling route' option of vpr with a variable?

[tangxifan]

yes. Refer to the use of ${OPENFPGA_VPR_DEVICE_LAYOUT}

[apond308]

Ok, also I needed to remove the '--activity_file ${ACTIVITY_FILE}' part of one of the 'link_openfpga_arch' line as well. Since that is not determined by the config, what would be the best way to resolve that besides creating a new script?