Merge pull request #134 from lnis-uofu/roman_dev

Fix typos causing the unknown `write_verilog_testbench` command errors
lnis-uofu · Feb 4, 2022 · e508bdd · e508bdd
2 parents 47b839f + bc43b6b
commit e508bdd
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Showing 3 changed files with 3 additions and 3 deletions.
diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_testbench.openfpga b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_testbench.openfpga
@@ -54,7 +54,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC \
-        --bitstream fabric_bitstream.bit
+        --bitstream fabric_bitstream.bit \
         --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
         --explicit_port_mapping
 # Exclude signal initialization since it does not help simulator converge

diff --git a/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga b/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga
@@ -55,7 +55,7 @@ write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC \
-        --bitstream fabric_bitstream.bit
+        --bitstream fabric_bitstream.bit \
         --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
         --explicit_port_mapping
 # Exclude signal initialization since it does not help simulator converge

diff --git a/FPGA1212_SOFA_PLUS_HD_PNR/FPGA1212_SOFA_PLUS_HD_task/generate_testbench.openfpga b/FPGA1212_SOFA_PLUS_HD_PNR/FPGA1212_SOFA_PLUS_HD_task/generate_testbench.openfpga
@@ -45,7 +45,7 @@ write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
 write_fabric_bitstream --format xml --file fabric_bitstream.xml
 
 write_full_testbench --file ./SRC \
-        --bitstream fabric_bitstream.bit
+        --bitstream fabric_bitstream.bit \
         --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
         --explicit_port_mapping