Merge branch 'devel'

hdl/modules/Manifest.py

@@ -3,6 +3,7 @@
 modules = { "local": [
         "fofb_ctrl_wrapper",
         "fofb_processing",
-        "fofb_sys_id"
+        "fofb_sys_id",
+        "fofb_shaper_filt"
     ]
 }

hdl/modules/fofb_ctrl_pkg.vhd

@@ -640,6 +640,31 @@ package fofb_ctrl_pkg is
     );
   end component;
 
+  component xwb_fofb_shaper_filt is
+    generic (
+      g_CHANNELS            : natural;
+      g_NUM_BIQUADS         : natural;
+      g_COEFF_INT_WIDTH     : natural;
+      g_COEFF_FRAC_WIDTH    : natural;
+      g_ARITH_EXTRA_BITS    : natural;
+      g_IFCS_EXTRA_BITS     : natural;
+      g_INTERFACE_MODE      : t_wishbone_interface_mode := CLASSIC;
+      g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
+      g_WITH_EXTRA_WB_REG   : boolean := false
+    );
+    port (
+      clk_i                 : in  std_logic;
+      rst_n_i               : in  std_logic;
+      sp_arr_i              : in  t_sp_arr(g_CHANNELS-1 DOWNTO 0);
+      sp_valid_arr_i        : in  std_logic_vector(g_CHANNELS-1 DOWNTO 0);
+      busy_arr_o            : out std_logic_vector(g_CHANNELS-1 DOWNTO 0);
+      filt_sp_arr_o         : out t_sp_arr(g_CHANNELS-1 DOWNTO 0);
+      filt_sp_valid_arr_o   : out std_logic_vector(g_CHANNELS-1 DOWNTO 0);
+      wb_slv_i              : in  t_wishbone_slave_in;
+      wb_slv_o              : out t_wishbone_slave_out
+    );
+  end component xwb_fofb_shaper_filt;
+
   component fofb_processing_dcc_adapter is
     generic (
       -- DCC packet FIFO depth
@@ -748,6 +773,23 @@ package fofb_ctrl_pkg is
     date          => x"20230504",
     name          => "FOFB_SYS_ID_REGS   ")));
 
+  -- FOFB shaper filters
+  constant c_xwb_fofb_shaper_filter_regs_sdb : t_sdb_device := (
+    abi_class     => x"0000",                   -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"00",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"4",                      -- 32-bit port granularity (0100)
+    sdb_component => (
+    addr_first    => x"0000000000000000",
+    addr_last     => x"000000000000FFFF",
+    product => (
+    vendor_id     => x"1000000000001215",       -- LNLS
+    device_id     => x"f65559b2",               -- Last 8 chars of "FOFB_SHAPER_REGS" md5sum
+    version       => x"00000001",
+    date          => x"20240419",
+    name          => "FOFB_SHAPER_REGS   ")));
+
 end fofb_ctrl_pkg;
 
 package body fofb_ctrl_pkg is

hdl/modules/fofb_processing/dot_prod_pkg.vhd

@@ -35,8 +35,8 @@ package dot_prod_pkg is
   type t_fofb_processing_sp_decim_arr is array (natural range <>) of signed(31 downto 0);
   type t_fofb_processing_sp_decim_ratio_arr is array (natural range <>) of integer range 0 to c_FOFB_SP_DECIM_MAX_RATIO;
 
-  constant c_FOFB_GAIN_INT_WIDTH         : natural := 3;
-  constant c_FOFB_GAIN_FRAC_WIDTH        : natural := 12;
+  constant c_FOFB_GAIN_INT_WIDTH         : natural := 0;
+  constant c_FOFB_GAIN_FRAC_WIDTH        : natural := 15;
   constant c_FOFB_GAIN_WIDTH             : natural := c_FOFB_GAIN_INT_WIDTH + c_FOFB_GAIN_FRAC_WIDTH + 1;
   constant c_FOFB_WB_GAIN_WIDTH          : natural := 32;
   type t_fofb_processing_gain_arr is array (natural range <>) of signed(c_FOFB_GAIN_WIDTH-1 downto 0);

hdl/modules/fofb_processing/fofb_processing_channel.vhd

@@ -197,10 +197,6 @@ begin
                                       - g_COEFF_FRAC_WIDTH
                                       - 1));
 
-  -- Cast gain_i to fixed point, assume the integer and fractionary parts to be
-  -- g_GAIN_INT_WIDTH and g_GAIN_FRAC_WIDTH respectively
-  gain <= sfixed(gain_i);
-
   -- Set-point output is the accumulator value casted to signed
   sp_o <= signed(to_slv(acc));
 
@@ -217,7 +213,7 @@ begin
       g_B_INT_WIDTH          => g_BPM_POS_INT_WIDTH,
       g_B_FRAC_WIDTH         => g_BPM_POS_FRAC_WIDTH,
       g_ACC_EXTRA_WIDTH      => g_DOT_PROD_ACC_EXTRA_WIDTH,
-      g_REG_INPUTS           => false,
+      g_REG_INPUTS           => true,
       g_MULT_PIPELINE_STAGES => g_DOT_PROD_MUL_PIPELINE_STAGES,
       g_ACC_PIPELINE_STAGES  => g_DOT_PROD_ACC_PIPELINE_STAGES
       )
@@ -249,6 +245,11 @@ begin
         sp_filtered <= (others => '0');
         sp_filtered_samples <= 0;
       else
+
+        -- Cast gain_i to fixed point, assume the integer and fractionary parts to be
+        -- g_GAIN_INT_WIDTH and g_GAIN_FRAC_WIDTH respectively
+        gain <= sfixed(gain_i);
+
         -- Delay 1 clock cycle to wait for the RAM data
         dot_prod_valid <= bpm_pos_err_valid_i;
         bpm_pos_err_fp <= sfixed(bpm_pos_err_i);

hdl/modules/fofb_shaper_filt/Manifest.py

@@ -0,0 +1,4 @@
+files = [
+    "cheby/wb_fofb_shaper_filt_regs.vhd",
+    "xwb_fofb_shaper_filt.vhd"
+]

hdl/modules/fofb_shaper_filt/cheby/build_cheby.sh

@@ -0,0 +1,4 @@
+#!/bin/bash
+
+mkdir -p doc
+cheby -i wb_fofb_shaper_filt_regs.cheby --hdl vhdl --gen-hdl wb_fofb_shaper_filt_regs.vhd --doc html --gen-doc doc/wb_fofb_shaper_filt_regs.html --gen-c wb_fofb_shaper_filt_regs.h --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd