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cheby: don't instantiate RAM for coeffs
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Instead of instantiating a "shadow" RAM for holding the coefficients,
simply access'em through a RAM interface. This optmizes resource usage
and might ease timing closure.

NOTE: The ABI wasn't broken. The only thing that's changed is the
      removal of the control register (no need to effectivate the
      coefficients anymore).
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@guilhermerc
guilhermerc committed Apr 11, 2024
1 parent 627e7e6 commit db6d1af
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107 changes: 0 additions & 107 deletions hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html
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Original file line number Diff line number Diff line change
Expand Up @@ -325,13 +325,6 @@ <h3>1. Memory map summary</h3>
<td class="td_code">coeffs_fp_repr</td>
<td class="td_code">coeffs_fp_repr</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x1008</td>
<td>REG</td>
<td><A href="#ctl">ctl</a></td>
<td class="td_code">ctl</td>
<td class="td_code">ctl</td>
</tr>
</table>

<h3><a name="sect_3_0">2. Register description</a></h3>
Expand Down Expand Up @@ -1366,106 +1359,6 @@ <h3>2.14. coeffs_fp_repr</h3>
</b>[<i>ro</i>]: Fractionary width.

</ul>
<a name="ctl"></a>
<h3>2.15. ctl</h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">ctl</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x1008</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">ctl</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x1008</td></tr>
</table>
<p>
Control register.<br>
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">eff_coeffs</td>
</tr>
</table>
<ul>
<li><b>
eff_coeffs
</b>[<i>rw</i>]: Strobe for effectivating (i.e. updating) coefficients.

<br>write 0: no effect<br>write 1: effectivates coefficients (this bit autoclears)
</ul>


</BODY>
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25 changes: 2 additions & 23 deletions hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby
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Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,7 @@ memory-map:
name: wb_fofb_shaper_filt_regs
description: Interface to FOFB IIR shaper filters regs
x-hdl:
busgroup: True
iogroup: wb_fofb_shaper_filt_regs_ifc
busgroup: true
children:
- repeat:
name: ch
Expand All @@ -13,6 +12,7 @@ memory-map:
- memory:
name: coeffs
memsize: 200
interface: sram
description: |
Coefficients for the ceil('max_filt_order'/2) IIR internal
biquads.
Expand All @@ -26,10 +26,6 @@ memory-map:
coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx}
coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx}

This array acts like a 'shadow' for the real coefficients and is
only effectivated when '1' is written to 'eff_coeffs' bit of
'ctl' register.

NOTE: This ABI supports up to 20th order filters, but only the
coefficients corresponding to the first 'max_filt_order' filters
are meaningful for the gateware.
Expand Down Expand Up @@ -68,20 +64,3 @@ memory-map:
range: 9-5
description: |
Fractionary width.
- reg:
name: ctl
width: 32
access: rw
description: |
Control register.
children:
- field:
name: eff_coeffs
x-hdl:
type: autoclear
range: 0
description: |
Strobe for effectivating (i.e. updating) coefficients.
comment: |
write 0: no effect
write 1: effectivates coefficients (this bit autoclears)
19 changes: 1 addition & 18 deletions hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
#ifndef __CHEBY__WB_FOFB_SHAPER_FILT_REGS__H__
#define __CHEBY__WB_FOFB_SHAPER_FILT_REGS__H__
#define WB_FOFB_SHAPER_FILT_REGS_SIZE 4108 /* 0x100c */
#define WB_FOFB_SHAPER_FILT_REGS_SIZE 4104 /* 0x1008 */

/* None */
#define WB_FOFB_SHAPER_FILT_REGS_CH 0x0UL
Expand All @@ -18,10 +18,6 @@ The 'coeffs' array should be populated in the following manner:
coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx}
coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx}
This array acts like a 'shadow' for the real coefficients and is
only effectivated when '1' is written to 'eff_coeffs' bit of
'ctl' register.
NOTE: This ABI supports up to 20th order filters, but only the
coefficients corresponding to the first 'max_filt_order' filters
are meaningful for the gateware.
Expand Down Expand Up @@ -50,11 +46,6 @@ represented decimal number.
#define WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_MASK 0x3e0UL
#define WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_SHIFT 5

/* Control register.
*/
#define WB_FOFB_SHAPER_FILT_REGS_CTL 0x1008UL
#define WB_FOFB_SHAPER_FILT_REGS_CTL_EFF_COEFFS 0x1UL

#ifndef __ASSEMBLER__
struct wb_fofb_shaper_filt_regs {
/* [0x0]: REPEAT (no description) */
Expand All @@ -71,10 +62,6 @@ The 'coeffs' array should be populated in the following manner:
coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx}
coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx}
This array acts like a 'shadow' for the real coefficients and is
only effectivated when '1' is written to 'eff_coeffs' bit of
'ctl' register.
NOTE: This ABI supports up to 20th order filters, but only the
coefficients corresponding to the first 'max_filt_order' filters
are meaningful for the gateware.
Expand Down Expand Up @@ -104,10 +91,6 @@ this register's content by 2**{32 - 'int_width'} to get the
represented decimal number.
*/
uint32_t coeffs_fp_repr;

/* [0x1008]: REG (rw) Control register.
*/
uint32_t ctl;
};
#endif /* !__ASSEMBLER__*/

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