Update DCC and infra-cores submodules, optimize timing further

Update CommsCtrlFPGA and infra-cores submodules to include the updated xci IP cores for Vivado 2022.2, add the ExtraTimingOpt flag to make timing closure possible.
lnls-dig · Apr 23, 2024 · ee5d2c7 · ee5d2c7
1 parent 7aace91
commit ee5d2c7
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Showing 3 changed files with 3 additions and 2 deletions.
diff --git a/hdl/ip_cores/CommsCtrlFPGA b/hdl/ip_cores/CommsCtrlFPGA
diff --git a/hdl/ip_cores/infra-cores b/hdl/ip_cores/infra-cores
diff --git a/hdl/syn/afcv4_ref_design/Manifest.py b/hdl/syn/afcv4_ref_design/Manifest.py
@@ -23,6 +23,7 @@
     ["steps.phys_opt_design.args.directive", "Explore"],
     ["steps.phys_opt_design.args.more options", "-verbose"],
     ["steps.phys_opt_design.is_enabled", "1"],
+    ["steps.place_design.args.directive", "ExtraTimingOpt"],
     ["steps.post_route_phys_opt_design.args.directive", "Explore"],
     ["steps.post_route_phys_opt_design.args.more options", "-verbose"],
     ["steps.post_route_phys_opt_design.is_enabled", "1"],
+0 −12		.gitignore
+0 −6		rtl/Manifest.py
+0 −5		rtl/chipscope/7series/Manifest.py
+0 −3,247		rtl/chipscope/7series/ila_fofb_cc_t8_d256_s16384/ila_fofb_cc_t8_d256_s16384.xci
+0 −3,251		rtl/chipscope/7series/ila_fofb_cc_t8_d256_s4096_cap/ila_fofb_cc_t8_d256_s4096_cap.xci
+0 −3,251		rtl/chipscope/7series/ila_fofb_cc_t8_d256_s8192_cap/ila_fofb_cc_t8_d256_s8192_cap.xci
+3 −2		rtl/fofb_cc_fa_if/Manifest.py
+281 −315		rtl/fofb_cc_fa_if/coregen/artix7/fofb_cc_fa_if_bram_16_to_32/fofb_cc_fa_if_bram_16_to_32.xci
+0 −929		rtl/fofb_cc_fa_if/coregen/artix7/fofb_cc_fa_if_bram_16_to_32/fofb_cc_fa_if_bram_16_to_32_sim_netlist.vhdl
+281 −314		rtl/fofb_cc_fa_if/coregen/artix7/fofb_cc_fa_if_bram_32_to_32/fofb_cc_fa_if_bram_32_to_32.xci
+0 −945		rtl/fofb_cc_fa_if/coregen/artix7/fofb_cc_fa_if_bram_32_to_32/fofb_cc_fa_if_bram_32_to_32_sim_netlist.vhdl
+2 −1		rtl/fofb_cc_rx_fifo/Manifest.py
+484 −574		rtl/fofb_cc_rx_fifo/coregen/artix7/fofb_cc_rx_fifo.xci
+0 −8,125		rtl/fofb_cc_rx_fifo/coregen/artix7/fofb_cc_rx_fifo_sim_netlist.vhdl
+2 −1		rtl/fofb_cc_tx_fifo/Manifest.py
+484 −581		rtl/fofb_cc_tx_fifo/coregen/artix7/fofb_cc_tx_fifo.xci
+0 −6,658		rtl/fofb_cc_tx_fifo/coregen/artix7/fofb_cc_tx_fifo_sim_netlist.vhdl
+589 −391		platform/xilinx/artix7/afc_v3/axi_datamover_0/axi_datamover_0.xci
+598 −402		platform/xilinx/artix7/afc_v3/axi_datamover_bpm/axi_datamover_bpm.xci
+895 −1,500		platform/xilinx/artix7/afc_v3/axi_interconnect/axi_interconnect.xci
+1,699 −1,520		platform/xilinx/artix7/afc_v3/axi_interconnect_bpm/axi_interconnect_bpm.xci
+589 −391		platform/xilinx/artix7/afc_v4/axi_datamover_0/axi_datamover_0.xci
+598 −402		platform/xilinx/artix7/afc_v4/axi_datamover_bpm/axi_datamover_bpm.xci
+895 −1,500		platform/xilinx/artix7/afc_v4/axi_interconnect/axi_interconnect.xci
+1,699 −1,520		platform/xilinx/artix7/afc_v4/axi_interconnect_bpm/axi_interconnect_bpm.xci
+6,301 −3,251		platform/xilinx/artix7/chipscope/ila_t8_d256_s4096_cap/ila_t8_d256_s4096_cap.xci
+6,301 −3,251		platform/xilinx/artix7/chipscope/ila_t8_d256_s8192_cap/ila_t8_d256_s8192_cap.xci
+1,632 −830		platform/xilinx/artix7/chipscope/vio_din2_w128_dout2_w128/vio_din2_w128_dout2_w128.xci
+1,632 −830		platform/xilinx/artix7/chipscope/vio_din2_w64_dout2_w64/vio_din2_w64_dout2_w64.xci