Update code from upstream repository https://github.com/pulp-
platform/riscv-dbg to revision
138d74bcaa90c70180c12215db3776813d2a95f2

* Update CHANGELOG.md (bluew)
* dm_csrs: Fix W1C behavior of `sberror` (Andreas Kurth)
* Add `xprop_off` to Xprop-incompatible processes (Andreas Kurth)
* debug_rom/gen_rom.py: Fix TypeError (Andreas Kurth)
* debug_rom/gen_rom.py: Fix indentation in p_outmux (Andreas Kurth)
* debug_rom/Makefile: Explicitly invoke `python3` (Andreas Kurth)
* Update CHANGELOG.md (bluew)
* tb: Handle unset VCS_HOME and VSIM_HOME seamlessly (bluew)
* tb: Simplify default tooling names (bluew)
* tb: Tie dangling ports (bluew)
* Update documentation (Christopher Reinwardt)
* [fix] Realign addresses to 64-bit (Christopher Reinwardt)
* Update CHANGELOG.md (bluew)
* tb: Ignore comb warnings (bluew)
* dmi_jtag: Update `dmi` `op` field based on DMI response (Andreas
  Kurth)
* dmi_jtag: Add mechanism for capturing failed DM op (Andreas Kurth)
* dmi_jtag: Set busy error only if no sticky error is set (Andreas
  Kurth)
* tb: Fix make vcsify (bluew)
* tb: Rewrite buggy openocd test script in Python (bluew)
* tb/Makefile: Use tabs (bluew)
* tb: Fix testbench build (bluew)
* dm_mem: Clear state of hart upon ndmreset (Andreas Kurth)
* dmi_jtag_tap: Bring all state to initial value in Test-Logic-Reset
  (Andreas Kurth)
* dmi_jtag: Take DMI response into account for reads (Andreas Kurth)
* dm_csrs: Return busy DMI response if SBA is busy (Andreas Kurth)
* dm_csrs: Return busy DMI response if command is busy (Andreas Kurth)
* dm_csrs: Put entire `dmi_resp_o` through FIFO (Andreas Kurth)
* dmi_jtag_tap: Use generic tech cells (Luca Colagrande)
* jtag_test: Add `read_dmi_exp_backoff()` and `sba_read_double()`
  functions (Luca Colagrande)
* Fix r/s/t/u-reset commands (epsilon)
* Update CHANGELOG.md (bluew)
* Re-align pins of dmi_bscane_tap with dmi_jtag_tap (Noah Huetter)
* Update CHANGELOG.md (bluew)
* Update changelog (Manuel Eggimann)
* Update JTAG Test package to reflect TestLogicReset fix (Manuel
  Eggimann)
* Make dmi_rst_ni synchronous in dm_csrs & filter glitches on
  dmi_rst_no (Manuel Eggimann)
* Bump to latest common cells version and add missing cdc port signals
  (Manuel Eggimann)
* Actually reset the dmi on remote_bitbang request (Manuel Eggimann)
* Modify tb to issue random dmi resets between transactions (Manuel
  Eggimann)
* Fix jtag DV IP to reset ir_select reg during reset (Manuel Eggimann)
* Fix wrong async reset connection and fix wrong dmi_clear logic
  (Manuel Eggimann)
* Fix syntax errors (Manuel Eggimann)
* Point to draft PR in common_cells for clearable CDC IPs (Manuel
  Eggimann)
* First draft of dmihardreset support and proper warm reset capability
  (Manuel Eggimann)
* Update CHANGELOG.md (bluew)
* [dm_sba] Fix verilator and ascentlint warnings (Michael Schaffner)
* [dm_sba] Move address increment arith out of the FSM (Michael
  Schaffner)
* [dm_sba/dm_csrs] Implement 'bad address' and 'other' error codes
  (Michael Schaffner)
* [dm_csrs] Correct reset value of sbcs register (Michael Schaffner)
* Address code review nits (Florian Zaruba)
* doc: Update documentation with OpenOCD configuration (Florian
  Zaruba)
* Add Xilinx BSCANE2 tap (Florian Zaruba)
* Revert "Merge pull request pulp-platform/riscv-dbg#111 from pulp-
  platform/feature/dmi-bscane" (bluew)
* sba: fix sberror reporting, [3] for unaligned access and [4] for
  unsupported size (Tzachi Noy)
* sba: shift sbdata_o accoring to be_idx for partial reads
  (sbacces8/16/...) (Tzachi Noy)
* sba: shift master_wdata_o to be aligned with master_be_o (Tzachi
  Noy)
* make sbaccess field writeable, and set value of
  sbacces8/16/32/64/128 according to BusWidth (Tzachi Noy)
* Fix for 64-bit accesses (Arjan Bink)
* Alternative fix for pull request 27 (Arjan Bink)

Signed-off-by: Greg Chadwick <[email protected]>

Update code from upstream repository
https://github.com/lowRISC/ibex.git to revision
c9f4a329636e59acb10647333badbb31bc7512b8

* [ci] introduce GitHub actions based private CI (Gary Guo)
* [rtl] Fix FI vulnerability in RF (Pascal Nasahl)
* [doc] Update cosim version (Pascal Nasahl)

Signed-off-by: Greg Chadwick <[email protected]>

Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
042415198f3dc6b3bc387c669c7e9cf982d208e2

Signed-off-by: Greg Chadwick <[email protected]>

This allows use of JTAG on systems with physical JTAG ports rather than
using the internal Xilinx BSCANE primitive.

This includes:
- Pin definitions in XDC file
- Modified build rules for FuseSoC
- A clock generator
- A top-level for Sonata
- A TCL file for Sonata

Co-authored-by: Marno van der Maas <[email protected]>

This is useful when wanting to program the Sonata board, which can now
be done using the following command:
```sh
./util/load_demo_system.sh run ./sw/c/build/demo/hello_world/demo ./util/sonata-openocd-cfg.tcl
```