The Repo is a 16-bit microprocessor based on a superscalar architecture with fetch width of two Instructions and four different pipelines in VHDL. The architecture is based on a Turing Complete ISA with 17 Instructions and was successfully verified by simulation using Modelsim.
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mohilp1998/superscalar_architecture
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A 16-bit Superscalar Architecture based on Turing Complete ISA with 17 instructions & 2 fetch width.
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