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nios_0.ptf.pre_generation_ptf
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nios_0.ptf.pre_generation_ptf
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SYSTEM nios_0
{
#
# Generated by: com.altera.sopcmodel.ensemble.EnsembleGeneratePTF
# Date: 2013.02.11.22:07:13
#
# clock_source "clk"
# altera_nios2 "cpu_0"
# altera_avalon_jtag_uart "jtag_uart_0"
# altera_avalon_new_sdram_controller "sdram_0"
# altera_avalon_tri_state_bridge "tri_state_bridge_0"
# altera_avalon_cfi_flash "cfi_flash_0"
# altera_avalon_timer "timer_0"
# altera_avalon_sysid "sysid"
# altera_avalon_uart "uart_0"
# altera_avalon_timer "timer_1"
# altera_avalon_lcd_16207 "lcd_16207_0"
# altera_avalon_pio "led_green"
# altera_avalon_pio "led_red"
# altera_avalon_pio "button_pio"
# altera_avalon_pio "switch_pio"
# user_logic_SEG7_LUT_8_classic "SEG7_Display"
# user_logic_SRAM_16Bits_512K_classic "sram_0"
# user_logic_Open_I2C_classic "I2C_0"
# altera_avalon_epcs_flash_controller "epcs_controller"
# altera_avalon_user_defined_interface_classic "ISP1362"
# user_logic_DM9000A_classic "DM9000A"
# altera_up_avalon_ps2_classic "ps2_0"
# binary_vga_controller "binary_vga_controller_0"
#
# Contains 56 connections.
#
System_Wizard_Version = "8.0";
Builder_Application = "sopc_builder_ca";
#. values for Builder_Application are:
#. sopc_builder_preview --> 6.1p, 7.0p prerelease versions
#. sopc_builder_ca --> 7.1 and later
#. (missing) --> 6.0 or earlier
WIZARD_SCRIPT_ARGUMENTS
{
hdl_language = "verilog";
device_family = "CYCLONEII";
device_family_id = "CYCLONEII";
generate_sdk = "0";
do_build_sim = "0";
hardcopy_compatible = "0";
CLOCKS
{
CLOCK clk
{
frequency = "50000000";
source = "External";
Is_Clock_Source = "0";
display_name = "clk";
pipeline = "0";
clock_module_connection_point_for_c2h = "clk.clk";
}
}
}
MODULE cpu_0
{
MASTER instruction_master
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT i_address
{
type = "address";
width = "25";
direction = "output";
Is_Enabled = "1";
}
PORT i_read
{
type = "read";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT i_readdata
{
type = "readdata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT i_readdatavalid
{
type = "readdatavalid";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT i_waitrequest
{
type = "waitrequest";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_resetrequest
{
type = "resetrequest";
width = "1";
direction = "output";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Do_Stream_Reads = "0";
Do_Stream_Writes = "0";
Max_Address_Width = "32";
Data_Width = "32";
Address_Width = "25";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Is_Instruction_Master = "1";
}
MEMORY_MAP
{
Entry cpu_0/jtag_debug_module
{
address = "0x01000000";
span = "0x00000800";
is_bridge = "0";
}
Entry sdram_0/s1
{
address = "0x00000000";
span = "0x00800000";
is_bridge = "0";
}
Entry cfi_flash_0/s1
{
address = "0x00800000";
span = "0x00100000";
is_bridge = "0";
}
Entry sram_0/avalonS
{
address = "0x00980000";
span = "0x00080000";
is_bridge = "0";
}
Entry epcs_controller/epcs_control_port
{
address = "0x00900800";
span = "0x00000800";
is_bridge = "0";
}
}
}
MASTER custom_instruction_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "nios_custom_instruction";
Data_Width = "32";
Address_Width = "8";
Is_Custom_Instruction = "1";
Is_Enabled = "0";
Max_Address_Width = "8";
}
PORT_WIRING
{
PORT dataa
{
type = "dataa";
width = "32";
direction = "output";
}
PORT datab
{
type = "datab";
width = "32";
direction = "output";
}
PORT result
{
type = "result";
width = "32";
direction = "input";
}
PORT clk_en
{
type = "clk_en";
width = "1";
direction = "output";
}
PORT reset
{
type = "reset";
width = "1";
direction = "output";
}
PORT start
{
type = "start";
width = "1";
direction = "output";
}
PORT done
{
type = "done";
width = "1";
direction = "input";
}
PORT n
{
type = "n";
width = "8";
direction = "output";
}
PORT a
{
type = "a";
width = "5";
direction = "output";
}
PORT b
{
type = "b";
width = "5";
direction = "output";
}
PORT c
{
type = "c";
width = "5";
direction = "output";
}
PORT readra
{
type = "readra";
width = "1";
direction = "output";
}
PORT readrb
{
type = "readrb";
width = "1";
direction = "output";
}
PORT writerc
{
type = "writerc";
width = "1";
direction = "output";
}
}
}
SLAVE jtag_debug_module
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "2048";
Read_Latency = "0";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Data_Width = "32";
Address_Width = "9";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Accepts_External_Connections = "1";
Requires_Internal_Connections = "";
MASTERED_BY cpu_0/instruction_master
{
priority = "1";
Offset_Address = "0x01000000";
}
MASTERED_BY cpu_0/data_master
{
priority = "1";
Offset_Address = "0x01000000";
}
Base_Address = "0x01000000";
}
PORT_WIRING
{
PORT jtag_debug_module_address
{
type = "address";
width = "9";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_begintransfer
{
type = "begintransfer";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_byteenable
{
type = "byteenable";
width = "4";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_debugaccess
{
type = "debugaccess";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT jtag_debug_module_select
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_write
{
type = "write";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
}
}
MASTER data_master
{
SYSTEM_BUILDER_INFO
{
Has_IRQ = "1";
Irq_Scheme = "individual_requests";
Bus_Type = "avalon";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Do_Stream_Reads = "0";
Do_Stream_Writes = "0";
Max_Address_Width = "32";
Data_Width = "32";
Address_Width = "25";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Is_Data_Master = "1";
}
PORT_WIRING
{
PORT d_irq
{
type = "irq";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT d_address
{
type = "address";
width = "25";
direction = "output";
Is_Enabled = "1";
}
PORT d_byteenable
{
type = "byteenable";
width = "4";
direction = "output";
Is_Enabled = "1";
}
PORT d_read
{
type = "read";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT d_readdata
{
type = "readdata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT d_readdatavalid
{
type = "readdatavalid";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT d_waitrequest
{
type = "waitrequest";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT d_write
{
type = "write";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT d_writedata
{
type = "writedata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT jtag_debug_module_debugaccess_to_roms
{
type = "debugaccess";
width = "1";
direction = "output";
Is_Enabled = "1";
}
}
MEMORY_MAP
{
Entry cpu_0/jtag_debug_module
{
address = "0x01000000";
span = "0x00000800";
is_bridge = "0";
}
Entry jtag_uart_0/avalon_jtag_slave
{
address = "0x01004000";
span = "0x00000008";
is_bridge = "0";
}
Entry sdram_0/s1
{
address = "0x00000000";
span = "0x00800000";
is_bridge = "0";
}
Entry cfi_flash_0/s1
{
address = "0x00800000";
span = "0x00100000";
is_bridge = "0";
}
Entry timer_0/s1
{
address = "0x00900000";
span = "0x00000020";
is_bridge = "0";
}
Entry sysid/control_slave
{
address = "0x00900020";
span = "0x00000008";
is_bridge = "0";
}
Entry uart_0/s1
{
address = "0x00900040";
span = "0x00000020";
is_bridge = "0";
}
Entry timer_1/s1
{
address = "0x00900060";
span = "0x00000020";
is_bridge = "0";
}
Entry lcd_16207_0/control_slave
{
address = "0x00900030";
span = "0x00000010";
is_bridge = "0";
}
Entry led_green/s1
{
address = "0x009000c0";
span = "0x00000010";
is_bridge = "0";
}
Entry led_red/s1
{
address = "0x009000d0";
span = "0x00000010";
is_bridge = "0";
}
Entry button_pio/s1
{
address = "0x00900120";
span = "0x00000010";
is_bridge = "0";
}
Entry switch_pio/s1
{
address = "0x00900130";
span = "0x00000010";
is_bridge = "0";
}
Entry SEG7_Display/avalonS
{
address = "0x00900028";
span = "0x00000004";
is_bridge = "0";
}
Entry sram_0/avalonS
{
address = "0x00980000";
span = "0x00080000";
is_bridge = "0";
}
Entry I2C_0/avalonS
{
address = "0x00900100";
span = "0x00000020";
is_bridge = "0";
}
Entry epcs_controller/epcs_control_port
{
address = "0x00900800";
span = "0x00000800";
is_bridge = "0";
}
Entry ISP1362/avalonS
{
address = "0x00900080";
span = "0x00000010";
is_bridge = "0";
}
Entry DM9000A/avalonS
{
address = "0x00900090";
span = "0x00000008";
is_bridge = "0";
}
Entry ps2_0/avalon_PS2_slave
{
address = "0x00900098";
span = "0x00000008";
is_bridge = "0";
}
Entry binary_vga_controller_0/avalon_slave_0
{
address = "0x00a00000";
span = "0x00200000";
is_bridge = "0";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
cache_has_dcache = "1";
cache_dcache_size = "2048";
cache_dcache_line_size = "4";
cache_dcache_bursts = "0";
cache_dcache_ram_block_type = "AUTO";
num_tightly_coupled_data_masters = "0";
gui_num_tightly_coupled_data_masters = "0";
gui_include_tightly_coupled_data_masters = "0";
gui_omit_avalon_data_master = "0";
cache_has_icache = "1";
cache_icache_size = "4096";
cache_icache_line_size = "32";
cache_icache_ram_block_type = "AUTO";
cache_icache_bursts = "0";
num_tightly_coupled_instruction_masters = "0";
gui_num_tightly_coupled_instruction_masters = "0";
gui_include_tightly_coupled_instruction_masters = "0";
debug_level = "2";
include_oci = "1";
oci_num_xbrk = "0";
oci_num_dbrk = "0";
oci_dbrk_trace = "0";
oci_dbrk_pairs = "0";
oci_onchip_trace = "0";
oci_offchip_trace = "0";
oci_data_trace = "0";
include_third_party_debug_port = "0";
oci_trace_addr_width = "7";
oci_debugreq_signals = "0";
oci_trigger_arming = "1";
oci_embedded_pll = "0";
oci_assign_jtag_instance_id = "0";
oci_jtag_instance_id = "0";
oci_num_pm = "0";
oci_pm_width = "32";
performance_counters_present = "0";
performance_counters_width = "32";
always_encrypt = "1";
debug_simgen = "0";
activate_model_checker = "0";
activate_test_end_checker = "0";
activate_trace = "1";
activate_monitors = "1";
clear_x_bits_ld_non_bypass = "1";
bit_31_bypass_dcache = "1";
hdl_sim_caches_cleared = "1";
hbreak_test = "0";
allow_full_address_range = "0";
extra_exc_info = "0";
branch_prediction_type = "Dynamic";
bht_ptr_sz = "8";
bht_index_pc_only = "0";
gui_branch_prediction_type = "Dynamic";
full_waveform_signals = "0";
export_pcb = "0";
big_endian = "0";
avalon_debug_port_present = "0";
illegal_instructions_trap = "0";
illegal_memory_access_detection = "0";
illegal_mem_exc = "0";
slave_access_error_exc = "0";
division_error_exc = "0";
eic_present = "0";
num_shadow_reg_sets = "0";
gui_mmu_present = "0";
mmu_present = "0";
process_id_num_bits = "8";
tlb_ptr_sz = "7";
tlb_num_ways = "16";
udtlb_num_entries = "6";
uitlb_num_entries = "4";
fast_tlb_miss_exc_slave = "";
fast_tlb_miss_exc_offset = "0x00000000";
mpu_present = "0";
mpu_num_data_regions = "8";
mpu_num_inst_regions = "8";
mpu_min_data_region_size_log2 = "12";
mpu_min_inst_region_size_log2 = "12";
mpu_use_limit = "0";
hardware_divide_present = "0";
gui_hardware_divide_setting = "0";
hardware_multiply_present = "1";
hardware_multiply_impl = "embedded_mul";
shift_rot_impl = "fast_le_shift";
gui_hardware_multiply_setting = "embedded_mul_fast_le_shift";
reset_slave = "epcs_controller/epcs_control_port";
break_slave = "cpu_0/jtag_debug_module";
exc_slave = "sdram_0/s1";
reset_offset = "0x00000000";
break_offset = "0x00000020";
exc_offset = "0x00000020";
cpu_reset = "0";
CPU_Implementation = "fast";
cpu_selection = "f";
device_family_id = "CYCLONEII";
address_stall_present = "1";
dsp_block_supports_shift = "0";
mrams_present = "0";
cpuid_value = "0";
dont_overwrite_cpuid = "1";
allow_legacy_sdk = "1";
legacy_sdk_support = "1";
inst_addr_width = "25";
data_addr_width = "25";
}
class = "altera_nios2";
class_version = "12.1";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Clock_Source = "clk";
Has_Clock = "1";
}
}
MODULE jtag_uart_0
{
SLAVE avalon_jtag_slave
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT rst_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_irq
{
type = "irq";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT av_chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_address
{
type = "address";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_read_n
{
type = "read_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT av_write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT av_waitrequest
{
type = "waitrequest";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT dataavailable
{
type = "dataavailable";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT readyfordata
{
type = "readyfordata";
width = "1";
direction = "output";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Has_IRQ = "1";
Bus_Type = "avalon";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "1";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Data_Width = "32";
Address_Width = "1";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
JTAG_Hub_Base_Id = "262254";
JTAG_Hub_Instance_Id = "0";
Connection_Limit = "1";
MASTERED_BY cpu_0/data_master
{
priority = "1";
Offset_Address = "0x01004000";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "1";
}
Base_Address = "0x01004000";
}
}
class = "altera_avalon_jtag_uart";
class_version = "12.1";
iss_model_name = "altera_avalon_jtag_uart";
WIZARD_SCRIPT_ARGUMENTS
{
allow_legacy_signals = "1";
write_depth = "64";
read_depth = "64";
write_threshold = "8";
read_threshold = "8";
read_char_stream = "";
showascii = "1";
relativepath = "1";
read_le = "0";
write_le = "0";
altera_show_unreleased_jtag_uart_features = "1";
}
SIMULATION
{
DISPLAY
{
SIGNAL av_chipselect
{
name = "av_chipselect";
}
SIGNAL av_address
{
name = "av_address";
}
SIGNAL av_read_n
{
name = "av_read_n";
}
SIGNAL av_readdata
{
name = "av_readdata";
radix = "hexadecimal";
}
SIGNAL av_write_n
{
name = "av_write_n";
}
SIGNAL av_writedata
{
name = "av_writedata";
radix = "hexadecimal";
}
SIGNAL av_waitrequest
{
name = "av_waitrequest";
}
SIGNAL dataavailable
{
name = "dataavailable";
}
SIGNAL readyfordata
{
name = "readyfordata";
}
}
INTERACTIVE_IN drive
{
enable = "0";
file = "_input_data_stream.dat";
mutex = "_input_data_mutex.dat";
log = "_in.log";
rate = "100";
signals = "temp,list";
exe = "nios2-terminal";
}
INTERACTIVE_OUT log
{
enable = "1";
exe = "perl -- atail-f.pl";
file = "_output_stream.dat";
radix = "ascii";
signals = "temp,list";
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Clock_Source = "clk";
Has_Clock = "1";
}
}
MODULE sdram_0
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT az_addr
{
type = "address";
width = "22";
direction = "input";
Is_Enabled = "1";
}
PORT az_be_n
{
type = "byteenable_n";
width = "2";
direction = "input";
Is_Enabled = "1";
}
PORT az_cs
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT az_data
{
type = "writedata";
width = "16";
direction = "input";
Is_Enabled = "1";
}
PORT az_rd_n
{