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Binary_VGA_Controller
Binary_VGA_Controller
 
 
altera_up_avalon_ps2
altera_up_avalon_ps2
 
 
db
db
 
 
nios_0_sim
nios_0_sim
 
 
software
software
 
 
user_logic_DM9000A
user_logic_DM9000A
 
 
user_logic_Open_I2C
user_logic_Open_I2C
 
 
user_logic_SEG7_LUT_8
user_logic_SEG7_LUT_8
 
 
user_logic_SRAM_16Bits_512K
user_logic_SRAM_16Bits_512K
 
 
Altera_UP_Avalon_PS2.v
Altera_UP_Avalon_PS2.v
 
 
Altera_UP_PS2.v
Altera_UP_PS2.v
 
 
Altera_UP_PS2_Command_Out.v
Altera_UP_PS2_Command_Out.v
 
 
Altera_UP_PS2_Data_In.v
Altera_UP_PS2_Data_In.v
 
 
DE2_NET.qpf
DE2_NET.qpf
 
 
DE2_NET.qsf
DE2_NET.qsf
 
 
DE2_NET.qws
DE2_NET.qws
 
 
DE2_NET.sof
DE2_NET.sof
 
 
DE2_NET.v
DE2_NET.v
 
 
DE2_NET_assignment_defaults.qdf
DE2_NET_assignment_defaults.qdf
 
 
DM9000A.v
DM9000A.v
 
 
DM9000A_IF.v
DM9000A_IF.v
 
 
I2C_0.v
I2C_0.v
 
 
ISP1362.v
ISP1362.v
 
 
Img_DATA.hex
Img_DATA.hex
 
 
Img_RAM.v
Img_RAM.v
 
 
Makefile
Makefile
 
 
README.md
README.md
 
 
Reset_Delay.v
Reset_Delay.v
 
 
SDRAM_PLL.v
SDRAM_PLL.v
 
 
SEG7_Display.v
SEG7_Display.v
 
 
SEG7_LUT.v
SEG7_LUT.v
 
 
SEG7_LUT_8.v
SEG7_LUT_8.v
 
 
SRAM_16Bit_512K.v
SRAM_16Bit_512K.v
 
 
VGA_Controller.v
VGA_Controller.v
 
 
VGA_NIOS_CTRL.v
VGA_NIOS_CTRL.v
 
 
VGA_OSD_RAM.v
VGA_OSD_RAM.v
 
 
VGA_Param.h
VGA_Param.h
 
 
binary_vga_controller_0.v
binary_vga_controller_0.v
 
 
button_pio.v
button_pio.v
 
 
cpu_0.ocp
cpu_0.ocp
 
 
cpu_0.sdc
cpu_0.sdc
 
 
cpu_0.v
cpu_0.v
 
 
cpu_0_bht_ram.mif
cpu_0_bht_ram.mif
 
 
cpu_0_dc_tag_ram.mif
cpu_0_dc_tag_ram.mif
 
 
cpu_0_ic_tag_ram.mif
cpu_0_ic_tag_ram.mif
 
 
cpu_0_jtag_debug_module_sysclk.v
cpu_0_jtag_debug_module_sysclk.v
 
 
cpu_0_jtag_debug_module_tck.v
cpu_0_jtag_debug_module_tck.v
 
 
cpu_0_jtag_debug_module_wrapper.v
cpu_0_jtag_debug_module_wrapper.v
 
 
cpu_0_mult_cell.v
cpu_0_mult_cell.v
 
 
cpu_0_oci_test_bench.v
cpu_0_oci_test_bench.v
 
 
cpu_0_ociram_default_contents.mif
cpu_0_ociram_default_contents.mif
 
 
cpu_0_rf_ram_a.mif
cpu_0_rf_ram_a.mif
 
 
cpu_0_rf_ram_b.mif
cpu_0_rf_ram_b.mif
 
 
cpu_0_test_bench.v
cpu_0_test_bench.v
 
 
epcs_controller.v
epcs_controller.v
 
 
epcs_controller_boot_rom_synth.hex
epcs_controller_boot_rom_synth.hex
 
 
i2c_master_bit_ctrl.v
i2c_master_bit_ctrl.v
 
 
i2c_master_byte_ctrl.v
i2c_master_byte_ctrl.v
 
 
i2c_master_defines.v
i2c_master_defines.v
 
 
i2c_master_top.v
i2c_master_top.v
 
 
jtag_uart_0.v
jtag_uart_0.v
 
 
lcd_16207_0.v
lcd_16207_0.v
 
 
led_green.v
led_green.v
 
 
led_red.v
led_red.v
 
 
nios_0.bsf
nios_0.bsf
 
 
nios_0.html
nios_0.html
 
 
nios_0.ptf
nios_0.ptf
 
 
nios_0.ptf.8.0
nios_0.ptf.8.0
 
 
nios_0.ptf.bak
nios_0.ptf.bak
 
 
nios_0.ptf.pre_generation_ptf
nios_0.ptf.pre_generation_ptf
 
 
nios_0.qip
nios_0.qip
 
 
nios_0.sopc
nios_0.sopc
 
 
nios_0.sopcinfo
nios_0.sopcinfo
 
 
nios_0.v
nios_0.v
 
 
nios_0_generation_script
nios_0_generation_script
 
 
nios_0_inst.v
nios_0_inst.v
 
 
nios_0_log.txt
nios_0_log.txt
 
 
ps2_0.v
ps2_0.v
 
 
sdram_0.v
sdram_0.v
 
 
sdram_0_test_component.v
sdram_0_test_component.v
 
 
sopc_add_qip_file.tcl
sopc_add_qip_file.tcl
 
 
sopc_builder_log.txt
sopc_builder_log.txt
 
 
sram_0.v
sram_0.v
 
 
switch_pio.v
switch_pio.v
 
 
sysid.v
sysid.v
 
 
timer_0.v
timer_0.v
 
 
timer_1.v
timer_1.v
 
 
uart_0.v
uart_0.v
 
 

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e4840_lab2

Embedded Systems Lab 2

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