CIF file converter

CSharp application for converting Caltech Intermediate Format (CIF) files to PNG images. CIF is a possible export option in Electric VLSI for exporting layouts.

Read INSTALL for build/install instructions.

Example

Cell in Electric VLSI:

Can be exported by choosing "File"->"Export"->"CIF (Caltech Intermediate Format)..." from the menu. Then running cifconv will result in the following PNG image.

cifconv --png dff_reg_bit_a.png dff_reg_bit_a.cif --width 400 --bg ffc0c0c0

Usage

cifconv [<OPTIONS>] [<FILES>]

<FILES> can be 0 or more input files in CIF format. If no input files are given, then standard input is read.

Options

Option	Description
‑‑png <FILE>	Specify output file <FILE> for PNG image generation. If <FILE> is -, standard output is used.
‑‑sym <SYMBOL>	Treat CIF input as library and draw only the given symbol <SYMBOL>. <SYMBOL> can either be the number of the symbol, or the name of the symbol if it was defined within the CIF input using the symbol name command (9). When this option is given, all shape and call commands outside of symbol definitions are ignored, so that only the shapes within the given symbol (and its sub symbol calls) are drawn.
‑‑style <STYLE>	Choose drawing style of PNG image. <STYLE> can be one of: electric‑cmos, electric‑mocmos (default), electric‑mocmos‑print, electric‑nmos, electric‑rcmos, electric‑rcmos‑print or mask
‑‑layer <LAYER>	Select one layer to operate on. If not given, all layers are selected.
‑‑whitelist <LAYERS>	List of layers to draw.
‑‑blacklist <LAYERS>	List of layers not to draw.
‑‑scale <SCALE>	Choose scale factor. If not given, a scale of 1.0 will be used, unless ‑‑width or ‑‑height is given. In that case, a scale factor is chosen, which makes everything fit into the given width/height frame.
‑‑origin-x <XCOORD>	Choose X coordinate of new origin point. This defines the X coordinate (after the scale factor is applied) of the top left corner of the output image. If not given, the min value (left boundary) of all X coordinates is taken, so that everything is visible in the output image.
‑‑origin-y <YCOORD>	Choose Y coordinate of new origin point. This defines the Y coordinate (after the scale factor is applied) of the top left corner of the output image. If not given, the max value (top boundary) of all Y coordinates is taken, so that everything is visible in the output image.
‑‑width <XSIZE>	Choose width of image in pixels. If not given, the image will be as wide as necessary to make everything visible with the given scale factor. If scale factor is not manually specified, then the maximum width will be 16,384 pixels and the scale factor will be adjusted to make the image fit.
‑‑height <YSIZE>	Choose height of image in pixels. If not given, the image will be as high as necessary to make everything visible with the given scale factor. If scale factor is not manually specified, then the maximum height will be 16,384 pixels and the scale factor will be adjusted to make the image fit.
‑‑bg <AARRGGBB>	Choose PNG background color. 00000000 is default.
‑‑at [png]<COORD>[@<LAYER>]	Highlight object(s) at coordinate at optionally given layer. If prefixed by png, coordinates are given in the transformed final image space.
‑‑roundgrowing	Use alternative rounding style instead of rounding to the nearest integer. For example, the corner coordinates of rectangular boxes will be rounded in a way that makes the box larger rather than smaller. The smaller one of the two corner coordinates are rounded down, the larger one is rounded up. This can help to reduce the likelihood of small unintentional gaps due to rounding, but it may cause misalignment of box corners with polygon corners.

Without any output options (like ‑‑png), the CIF inputs are still read and checked for errors.

‑‑layer can be used to select a single layer for drawing. ‑‑whitelist can be used to select multiple layers to be drawn. The difference between the two is, ‑‑whitelist will only draw layers that are supported by the selected drawing style (‑‑style), whereas ‑‑layer will force a layer to be drawn, even if it is not supported by the selected drawing style. In the latter case, unsupported layers are usually drawn in solid black. If neither ‑‑layer nor ‑‑whitelist is given, all layers supported by the selected drawing style are drawn, except for those listed by ‑‑blacklist. ‑‑blacklist has precedence over ‑‑whitelist.

Coordinates of each shape in the CIF will be transformed in the following order:

1. Scale factor is applied. If scale factor is not specified by ‑‑scale option, then scale factor is determined automatically to make the image fit into bounds given by ‑‑width and ‑‑height options.
2. Origin translation is applied. If ‑‑origin-(x|y) options are not specified, then origin is determined automatically to shift everything into the visible bounds of the output image.
3. Invert Y coordinate. (CIF Y coordinates grow from bottom to top. Image Y coordinates grow from top to bottom.)

Layers

The following table describes all layers and which CIF layers are being mapped to them.

Layer	From CIF	Description
active	CAA, CD	Active/diffusion area with unspecified doping. In most fabrication technologies, this layer describes P and N doped active areas. It is usually where no insulation (SiO2) is grown. The actual doping is then chosen later in the process by the p‑select and n‑select layers.
p‑active	CAP	P doped active/diffusion area.
n‑active	CAN	N doped active/diffusion area.
select	CSG	Selection mask for stronger ion bombardment with unspecified direction (P/N).
p‑select	CSP, CS	Selection mask for stronger ion bombardment for P doping active areas.
n‑select	CSN	Selection mask for stronger ion bombardment for N doping active areas.
well	CWG	Well with unspecified doping.
p‑well	CWP, CW	P doped well.
n‑well	CWN	N doped well.
poly	CPG, CP, NP	Polysilicon 1 layer. This is the lowest polysilicon layer. It can function as transistor gates.
electrode	CEL	Polysilicon 2 layer. Often used as electrode of capacitors, hence the name.
metal1	CMF, CM, NM	Metal 1 layer. The lowest metal layer. The only metal layer that can make contact down to poly or active.
metal2	CMS	Metal 2 layer.
metal3	CMT	Metal 3 layer.
metal4	CMQ	Metal 4 layer.
metal5	CMP	Metal 5 layer.
metal6	CM6	Metal 6 layer.
contact	CCG, CCC, CC, NC	Contact between metal 1, polysilicon/electrode and active layers. Many technologies don't differentiate between poly and active contacts. Contacts are also known as cuts.
active‑contact	CCA	Contact between metal 1 and active layer.
poly‑contact	CCP	Contact between metal 1 and polysilicon 1 layer.
electrode‑contact	CCE	Contact between metal 1 and polysilicon 2 (aka. electrode) layer.
oversize‑contact	NO	The NMOS technology in Electric VLSI has this layer. Oversized contacts between metal 1 and poly or active probably need special handling in some fabrication technologies.
buried	CCD, NB	Opening in the insulation between active and polysilicon 1. Used to create buried contacts between those layers without the need to connect both to metal 1.
via1	CVA	Via 1 layer. Connection between metal 1 and metal 2. For some technologies, this layer may be used for all vias, in which case vias will connect from metal 1 all the way through to the highest metal layer.
via2	CVS	Via 2 layer. Connection between metal 2 and metal 3.
via3	CVT	Via 3 layer. Connection between metal 3 and metal 4.
via4	CVQ	Via 4 layer. Connection between metal 4 and metal 5.
via5	CV5	Via 5 layer. Connection between metal 5 and metal 6.
p‑high‑voltage	CVP	Defined in the MOSIS SCMOS Design Rules.
n‑high‑voltage	CVN	Defined in the MOSIS SCMOS Design Rules.
thick‑active	CTA	Used by Electric VLSI to define a wider area around the select layer of thick P/N MOS transistors, which are called high-voltage resistors in the log.
mems‑open	COP	Defined in the MOSIS SCMOS Design Rules.
mems‑etch‑stop	CPS	Defined in the MOSIS SCMOS Design Rules.
pad	CX, XP	Bonding or test pad.
exp‑field‑impl	CFI	Defined in the MOSIS SCMOS Design Rules.
poly‑cap	CPC	Defined in the MOSIS SCMOS Design Rules.
silicide‑block	CSB	Silicide block layer. Normally, the conductivity of polysilicon is improved by silicidation. For polysilicon resistors, this silicidation can be blocked to give them a higher resistance.
passivation	COG, CG, NG	Passivation layer mask is used to define openings in the insulating and protecting layer at the top of the chip (aka. overglass). These openings are usually where bonding pads and test pads are.
p‑base	CBA	P doped base of vertical bipolar NPN transistors in MOSIS SCMOS technology with analog option.
cap‑well	CWC	Defined in the MOSIS SCMOS Design Rules.
implant	NI	Implant area of depletion mode transistors in NMOS technologies.
light‑implant	NJ	Can be used in Electric VLSI when layouting NMOS technology cells, but there are no transistor primitives using this layer.
hard‑enhancement	NE	Can be used in Electric VLSI when layouting NMOS technology cells, but there are no transistor primitives using this layer.
light‑enhancement	NF	Can be used in Electric VLSI when layouting NMOS technology cells, but there are no transistor primitives using this layer.
hi‑res	CHR	Used by Electric VLSI on polysilicon 2 resistors, probably to change the thickness or conductivity of polysilicon 2 to tune the resistance
selected	-	Layer created by cifconv for drawing highlights over elements selected by the ‑‑at option.

Drawing styles

Table with all drawing styles that can be specified when using the ‑‑style option:

Style	Description
electric‑cmos	Electric VLSI CMOS technology. Draws the following layers: metal1, poly, active, p‑active, n‑active, select, p‑select, well, p‑well, contact, oversize‑contact, active‑contact, poly‑contact, electrode‑contact, passivation and selected
electric‑mocmos	Electric VLSI MoCMOS technology. Draws the following layers: metal1, poly, silicide‑block, active, p‑active, n‑active, metal2, metal3, contact, oversize‑contact, active‑contact, poly‑contact, electrode‑contact, via1, via2, via3, via4, via5, pad, hi‑res, select, n‑select, p‑high‑voltage, n‑high‑voltage, thick‑active, passivation, poly‑cap, well, n‑well, p‑well, p‑base, p‑select, electrode, metal4, metal5, metal6 and selected
electric‑mocmos‑print	Electric VLSI MoCMOS technology like it appears when printing. Draws the following layers: metal1, poly, silicide‑block, active, p‑active, n‑active, metal2, metal3, contact, oversize‑contact, active‑contact, poly‑contact, electrode‑contact, via1, via2, via3, via4, via5, pad, hi‑res, select, n‑select, p‑high‑voltage, n‑high‑voltage, thick‑active, passivation, poly‑cap, well, n‑well, p‑well, p‑base, p‑select, electrode, metal4, metal5, metal6 and selected
electric‑nmos	Electric VLSI NMOS technology. Draws the following layers: metal1, poly, active, p‑active, n‑active, implant, buried, contact, active‑contact, poly‑contact, electrode‑contact, oversize‑contact, passivation, hard‑enhancement, light‑implant, light‑enhancement and selected
electric‑rcmos	Electric VLSI RCMOS technology. Draws the following layers: metal1, poly, active, p‑active, n‑active, well, metal2, contact, oversize‑contact, active‑contact, poly‑contact, electrode‑contact, via1, passivation, select and selected
electric‑rcmos‑print	Electric VLSI RCMOS technology like it appears when printing. Draws the following layers: metal1, poly, active, p‑active, n‑active, well, metal2, contact, oversize‑contact, active‑contact, poly‑contact, electrode‑contact, via1, passivation, select and selected
mask	Just draws all layers in solid black. Use the ‑‑layer option to select a single layer for generating a mask for that layer.