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| */*/config.old | ||
| */*/rootfs_config.old | ||
| build/ | ||
| images/linux/ | ||
| pre-built/linux/ | ||
| .petalinux/* | ||
| !.petalinux/metadata | ||
| *.o | ||
| *.jou | ||
| *.log | ||
| /components/plnx_workspace | ||
| /components/yocto |
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| PETALINUX_VER=2022.2 | ||
| VALIDATE_HW_CHKSUM=1 | ||
| HDF_EXT=xsa | ||
| HARDWARE_CHECKSUM=69efc480b3fae825df5e85c136936db9 | ||
| YOCTO_SDK=4ade5db6317c61f6cb657b7a919dfa25 | ||
| RFSCONFIG_CHKSUM=026f30da1c10b8757c32bb5536c7be4c | ||
| HARDWARE_PATH=/home/dnicholes/Projects/lightning-dev-base/platform/ZCU111_petalinux/hardware/imp/top.xsa |
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| all: | ||
| # petalinux-config --silentconfig --get-hw-description ../hardware/imp/top.xsa | ||
| # petalinux-build -c pmu-firmware -c fsbl-firmware -c device-tree -x cleansstate | ||
| # petalinux-build -c pmu-firmware -c fsbl-firmware -c device-tree | ||
| petalinux-build -c pmu-firmware -x cleansstate | ||
| petalinux-build -c pmu-firmware | ||
| petalinux-build -c fsbl-firmware -x cleansstate | ||
| petalinux-build -c fsbl-firmware |
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| ########################################################################## | ||
| This is a brief document containing design specific details for : xilinx-zcu111-2022.2 | ||
| This is auto-generated by Petalinux ref-design builder created @ Fri Oct 14 16:43:07 MDT 2022 | ||
| ########################################################################## | ||
| BOARD: xilinx.com:zcu111:part0:1.4 | ||
| BLOCK DESIGN: custom | ||
| ------------------------------------------------------------------------------------------------------------------------------------------------------ | ||
| MODULE INSTANCE NAME IP TYPE IP VERSION IP | ||
| ------------------------------------------------------------------------------------------------------------------------------------------------------ | ||
| project_1_adc_sink_i_0 exdes_rfadc_data_sink 1.0 xilinx.com:module_ref:exdes_rfadc_data_sink:1.0 | ||
| project_1_axi_gpio_0 axi_gpio 2.0 xilinx.com:ip:axi_gpio:2.0 | ||
| project_1_axi_intc_0 axi_intc 4.1 xilinx.com:ip:axi_intc:4.1 | ||
| project_1_axi_interconnect_0_0 axi_interconnect 2.1 xilinx.com:ip:axi_interconnect:2.1 | ||
| project_1_chan_ctrl_fifo_0 axis_data_fifo 2.0 xilinx.com:ip:axis_data_fifo:2.0 | ||
| project_1_chan_ctrl_reg_0 axis_register_slice 1.1 xilinx.com:ip:axis_register_slice:1.1 | ||
| project_1_clk_wiz_0 clk_wiz 6.0 xilinx.com:ip:clk_wiz:6.0 | ||
| project_1_concat_int_0 xlconcat 2.1 xilinx.com:ip:xlconcat:2.1 | ||
| project_1_const_1_0 xlconstant 1.1 xilinx.com:ip:xlconstant:1.1 | ||
| project_1_dac_source_i_0 exdes_rfdac_src 1.0 xilinx.com:module_ref:exdes_rfdac_src:1.0 | ||
| project_1_data_source_0 data_source_top 1.0 xilinx.com:hls:data_source_top:1.0 | ||
| project_1_dec_add_keep_0 add_keep_128 1.0 xilinx.com:hls:add_keep_128:1.0 | ||
| project_1_dec_add_keep_trim_0 axis_subset_converter 1.1 xilinx.com:ip:axis_subset_converter:1.1 | ||
| project_1_dec_ctrl_fifo_0 axis_data_fifo 2.0 xilinx.com:ip:axis_data_fifo:2.0 | ||
| project_1_dec_ctrl_reg_0 axis_register_slice 1.1 xilinx.com:ip:axis_register_slice:1.1 | ||
| project_1_dec_ctrl_reinterpret_0 axis_subset_converter 1.1 xilinx.com:ip:axis_subset_converter:1.1 | ||
| project_1_dec_data_reinterpret_0 axis_subset_converter 1.1 xilinx.com:ip:axis_subset_converter:1.1 | ||
| project_1_dec_ip_mon_0 monitor 1.0 xilinx.com:hls:monitor:1.0 | ||
| project_1_dec_ip_probe_0 axis_probe 1.0 xilinx.com:user:axis_probe:1.0 | ||
| project_1_dec_keep_ctrl_fifo_0 axis_data_fifo 2.0 xilinx.com:ip:axis_data_fifo:2.0 | ||
| project_1_dec_op_mon_0 monitor 1.0 xilinx.com:hls:monitor:1.0 | ||
| project_1_dec_op_probe_0 axis_probe 1.0 xilinx.com:user:axis_probe:1.0 | ||
| project_1_dec_stat_reinterpret_0 axis_subset_converter 1.1 xilinx.com:ip:axis_subset_converter:1.1 | ||
| project_1_demod_0 demod_4x 1.0 xilinx.com:hls:demod_4x:1.0 | ||
| project_1_enc_add_keep_0 add_keep_128 1.0 xilinx.com:hls:add_keep_128:1.0 | ||
| project_1_enc_add_keep_trim_0 axis_subset_converter 1.1 xilinx.com:ip:axis_subset_converter:1.1 | ||
| project_1_enc_ctrl_reinterpret_0 axis_subset_converter 1.1 xilinx.com:ip:axis_subset_converter:1.1 | ||
| project_1_enc_data_fifo_0 axis_data_fifo 2.0 xilinx.com:ip:axis_data_fifo:2.0 | ||
| project_1_enc_data_reinterpret_0 axis_subset_converter 1.1 xilinx.com:ip:axis_subset_converter:1.1 | ||
| project_1_enc_ip_mon_0 monitor 1.0 xilinx.com:hls:monitor:1.0 | ||
| project_1_enc_ip_probe_0 axis_probe 1.0 xilinx.com:user:axis_probe:1.0 | ||
| project_1_enc_keep_ctrl_fifo_0 axis_data_fifo 2.0 xilinx.com:ip:axis_data_fifo:2.0 | ||
| project_1_enc_op_mon_0 monitor 1.0 xilinx.com:hls:monitor:1.0 | ||
| project_1_enc_op_probe_0 axis_probe 1.0 xilinx.com:user:axis_probe:1.0 | ||
| project_1_gpio_reset_0 axi_gpio 2.0 xilinx.com:ip:axi_gpio:2.0 | ||
| project_1_hard_chan_data_fifo_0 axis_data_fifo 2.0 xilinx.com:ip:axis_data_fifo:2.0 | ||
| project_1_hard_data_reg_0 axis_register_slice 1.1 xilinx.com:ip:axis_register_slice:1.1 | ||
| project_1_llr_reinterpret_0 axis_subset_converter 1.1 xilinx.com:ip:axis_subset_converter:1.1 | ||
| project_1_llr_reshape_0 axis_dwidth_converter 1.1 xilinx.com:ip:axis_dwidth_converter:1.1 | ||
| project_1_mod_and_chan_0 mod_and_chan_4x 1.0 xilinx.com:hls:mod_and_chan_4x:1.0 | ||
| project_1_reset_slice_0 xlslice 1.0 xilinx.com:ip:xlslice:1.0 | ||
| project_1_rst_clk_wiz_100M_0 proc_sys_reset 5.0 xilinx.com:ip:proc_sys_reset:5.0 | ||
| project_1_rst_clk_wiz_300M_0 proc_sys_reset 5.0 xilinx.com:ip:proc_sys_reset:5.0 | ||
| project_1_rst_zynq_ultra_ps_e_0_99M_0 proc_sys_reset 5.0 xilinx.com:ip:proc_sys_reset:5.0 | ||
| project_1_rtc_0 c_counter_binary 12.0 xilinx.com:ip:c_counter_binary:12.0 | ||
| project_1_sd_fec_dec_0 sd_fec 1.1 xilinx.com:ip:sd_fec:1.1 | ||
| project_1_sd_fec_enc_0 sd_fec 1.1 xilinx.com:ip:sd_fec:1.1 | ||
| project_1_src_data_broadcast_0 axis_broadcaster 1.1 xilinx.com:ip:axis_broadcaster:1.1 | ||
| project_1_src_data_fifo_0 axis_data_fifo 2.0 xilinx.com:ip:axis_data_fifo:2.0 | ||
| project_1_stats_0 stats_top 1.0 xilinx.com:hls:stats_top:1.0 | ||
| project_1_usp_rf_data_converter_0_i_0 usp_rf_data_converter 2.6 xilinx.com:ip:usp_rf_data_converter:2.6 | ||
| project_1_zynq_ultra_ps_e_0_0 zynq_ultra_ps_e 3.4 xilinx.com:ip:zynq_ultra_ps_e:3.4 | ||
| project_1_zynq_ultra_ps_e_0_axi_periph_0 axi_interconnect 2.1 xilinx.com:ip:axi_interconnect:2.1 |