Fixed simulation, minor bugs

Ambient light sensor project is now building correctly in icecube. S
nandland · Mar 16, 2019 · 02ae8b3 · 02ae8b3
1 parent 178f3d7
commit 02ae8b3
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Showing 3 changed files with 23 additions and 25 deletions.
diff --git a/VHDL/sim/SPI_Master_With_Single_CS_TB.vhd b/VHDL/sim/SPI_Master_With_Single_CS_TB.vhd
@@ -44,7 +44,7 @@ architecture TB of SPI_Master_With_Single_CS_TB is
     o_dv   <= '0';
     wait until rising_edge(w_Master_TX_Ready);
   end procedure SendSingleByte;
-  
+
 begin  -- architecture TB
 
   -- Clock Generators:
@@ -58,22 +58,22 @@ begin  -- architecture TB
       MAX_BYTES_PER_CS  => MAX_BYTES_PER_CS,
       CS_INACTIVE_CLKS  => CS_INACTIVE_CLKS)
     port map (
-      i_Rst_L    => i_Rst_L,
-      i_Clk      => i_Clk,
+      i_Rst_L    => r_Rst_L,
+      i_Clk      => r_Clk,
       -- TX (MOSI) Signals
-      i_TX_Count => i_TX_Count,     -- Number of bytes per CS         
-      i_TX_Byte  => i_TX_Byte,      -- Byte to transmit on MOSI       
-      i_TX_DV    => i_TX_DV,        -- Data Valid Pulse with i_TX_Byte
-      o_TX_Ready => o_TX_Ready,     -- Transmit Ready for Byte        
+      i_TX_Count => r_Master_TX_Count,  -- Number of bytes per CS         
+      i_TX_Byte  => r_Master_TX_Byte,   -- Byte to transmit on MOSI       
+      i_TX_DV    => r_Master_TX_DV,     -- Data Valid Pulse with i_TX_Byte
+      o_TX_Ready => w_Master_TX_Ready,  -- Transmit Ready for Byte        
       -- RX (MISO) Signals
-      o_RX_Count => o_RX_Count,     -- Index of RX'd byte              
-      o_RX_DV    => o_RX_DV,        -- Data Valid pulse (1 clock cycle)
-      o_RX_Byte  => o_RX_Byte,      -- Byte received on MISO           
+      o_RX_Count => w_Master_RX_Count,  -- Index of RX'd byte              
+      o_RX_DV    => w_Master_RX_DV,     -- Data Valid pulse (1 clock cycle)
+      o_RX_Byte  => w_Master_RX_Byte,   -- Byte received on MISO           
       -- SPI Interface
-      o_SPI_Clk  => o_SPI_Clk,
-      i_SPI_MISO => i_SPI_MISO,
-      o_SPI_MOSI => o_SPI_MOSI,
-      o_SPI_CS_n => o_SPI_CS_n
+      o_SPI_Clk  => w_SPI_Clk,
+      i_SPI_MISO => w_SPI_MOSI,
+      o_SPI_MOSI => w_SPI_MOSI,
+      o_SPI_CS_n => w_SPI_CS_n
       );
 
   Testing : process is
@@ -86,7 +86,7 @@ begin  -- architecture TB
     -- Test sending 2 bytes
     SendSingleByte(X"C1", r_Master_TX_Byte, r_Master_TX_DV);
     report "Sent out 0xC1, Received 0x" & to_hstring(unsigned(w_Master_RX_Byte));
-    SendSingleByte(X"C1", r_Master_TX_Byte, r_Master_TX_DV);
+    SendSingleByte(X"C2", r_Master_TX_Byte, r_Master_TX_DV);
     report "Sent out 0xC2, Received 0x" & to_hstring(unsigned(w_Master_RX_Byte)); 
     wait for 100 ns;
     assert false report "Test Complete" severity failure;

diff --git a/VHDL/source/SPI_Master.vhd b/VHDL/source/SPI_Master.vhd
@@ -162,11 +162,11 @@ begin
         r_TX_Bit_Count <= "111";
 
       -- Catch the case where we start transaction and CPHA = 0
-      elsif r_TX_DV and not w_CPHA then
+      elsif (r_TX_DV = '1' and w_CPHA = '0') then
         o_SPI_MOSI     <= r_TX_Byte(7);
         r_TX_Bit_Count <= "110";        -- 6
-      elsif (r_Leading_Edge and w_CPHA) or (r_Trailing_Edge and not w_CPHA) then
-        r_TX_Bit_Count <= r_TX_Bit_Count - '1';
+      elsif (r_Leading_Edge = '1' and w_CPHA = '1') or (r_Trailing_Edge = '1' and w_CPHA = '0') then
+        r_TX_Bit_Count <= r_TX_Bit_Count - 1;
         o_SPI_MOSI     <= r_TX_Byte(to_integer(r_TX_Bit_Count));
       end if;
     end if;
@@ -186,9 +186,9 @@ begin
 
       if o_TX_Ready = '1' then -- Check if ready, if so reset count to default
         r_RX_Bit_Count <= "111";        -- Starts at 7
-      elsif (r_Leading_Edge and not w_CPHA) or (r_Trailing_Edge and w_CPHA) then
+      elsif (r_Leading_Edge = '1' and w_CPHA = '0') or (r_Trailing_Edge = '1' and w_CPHA = '1') then
         o_RX_Byte(to_integer(r_RX_Bit_Count)) <= i_SPI_MISO;  -- Sample data
-        r_RX_Bit_Count <= r_RX_Bit_Count - '1';
+        r_RX_Bit_Count <= r_RX_Bit_Count - 1;
         if r_RX_Bit_Count = "000" then
           o_RX_DV <= '1';   -- Byte done, pulse Data Valid
         end if;

diff --git a/VHDL/source/SPI_Master_With_Single_CS.vhd b/VHDL/source/SPI_Master_With_Single_CS.vhd
@@ -80,7 +80,7 @@ architecture RTL of SPI_Master_With_Single_CS is
 begin
 
   -- Instantiate Master
-  SPI_Master_1: entity work.SPI_Master
+  SPI_Master_1 : entity work.SPI_Master
     generic map (
       SPI_MODE          => SPI_MODE,
       CLKS_PER_HALF_BIT => CLKS_PER_HALF_BIT)
@@ -91,7 +91,7 @@ begin
       -- TX (MOSI) Signals
       i_TX_Byte  => i_TX_Byte,          -- Byte to transmit
       i_TX_DV    => i_TX_DV,            -- Data Valid pulse
-      o_TX_Ready => o_TX_Ready,         -- Transmit Ready for Byte
+      o_TX_Ready => w_Master_Ready,     -- Transmit Ready for Byte
       -- RX (MISO) Signals
       o_RX_DV    => o_RX_DV,            -- Data Valid pulse
       o_RX_Byte  => o_RX_Byte,          -- Byte received on MISO
@@ -163,9 +163,7 @@ begin
 
   o_SPI_CS_n <= r_CS_n;
 
-  o_TX_Ready <= '1' when (r_SM_CS = IDLE) or (r_SM_CS = TRANSFER and w_Master_Ready = '1' and r_TX_Count > 0) and i_TX_DV != '1' else '0'; 
-
-  --assign o_TX_Ready  = ((r_SM_CS == IDLE) | (r_SM_CS == TRANSFER && w_Master_Ready == 1'b1 && r_TX_Count > 0)) & ~i_TX_DV;
+  o_TX_Ready <= '1' when i_TX_DV /= '1' and ((r_SM_CS = IDLE) or (r_SM_CS = TRANSFER and w_Master_Ready = '1' and r_TX_Count > 0)) else '0'; 
 
 end architecture RTL;