mediatek: add build for MT7981 RFB

Add build for the MTK3943 reference board for MT7981B+MT7976C.

**Hardware specification:**

 - SoC: MediaTek MT7981B 2x A53
 - Flash: various options
 - RAM: 256MB DDR3
 - Ethernet: 4 x 10/100/1000 Mbps via MT7531AE switch
        EITHER 1 x 10/100/1000 Mbps built-in PHY
            OR 1 x 10/100/1000/2500 Mbps MaxLinear GPY211C
 - Switch: MediaTek MT7531AE
 - WiFi: MediaTek MT7976C
 - Button: RST, WPS

**Flash instructions for SPIM-NAND:**
 - write *mt7981-rfb-spim-nand-preloader.bin to 'BL2' partition
 - write *mt7981-rfb-spim-nand-bl31-uboot.fip to 'FIP' partition
 - erase 'ubi' partition
 - reset board
 - create ubootenv and ubootenv2 UBI volumes in U-Boot
 - edit environment and set bootcmd, e.g.
   setenv bootconf 'config-1#mt7981-rfb-spim-nand#mt7981-rfb-mxl-2p5g-phy-eth1'
   setenv bootcmd 'ubi read $loadaddr fit; bootm $loadaddr#$bootconf'
 - load initramfs image via TFTP:
   setenv serverip 192.168.1.254
   setenv ipaddr 192.168.1.1
   setenv bootfile openwrt-mediatek-filogic-mediatek_mt7981-rfb-initramfs.itb
   saveenv ; saveenv
   tftpboot
   bootm $loadaddr#$bootconf
 - Now use sysupgrade to write OpenWrt firmware to flash.

SNFI-NAND, SPIM-NOR and eMMC all work very similar, a bootable SD card image
is also being generated. However, as the board I've been provided only comes
with SPIM-NAND all other boot media are untested.

Signed-off-by: Daniel Golle <[email protected]>
(cherry picked from commit ce7209b)

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
+
+	fragment@0 {
+		target = <&gmac1>;
+		__overlay__ {
+			phy-mode = "2500base-x";
+			phy-handle = <&phy5>;
+		};
+	};
+
+	fragment@1 {
+		target = <&mdio_bus>;
+		__overlay__ {
+			reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
+			reset-delay-us = <600>;
+			reset-post-delay-us = <20000>;
+
+			phy5: ethernet-phy@5 {
+				reg = <5>;
+				compatible = "ethernet-phy-ieee802.3-c45";
+				phy-mode = "2500base-x";
+			};
+		};
+	};
+};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso

@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
+
+	fragment@0 {
+		target = <&sw_p5>;
+		__overlay__ {
+			phy-mode = "2500base-x";
+			phy-handle = <&phy5>;
+			status = "okay";
+		};
+	};
+
+	fragment@1 {
+		target = <&mdio_bus>;
+		__overlay__ {
+			reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
+			reset-delay-us = <600>;
+			reset-post-delay-us = <20000>;
+
+			phy5: ethernet-phy@5 {
+				reg = <5>;
+				compatible = "ethernet-phy-ieee802.3-c45";
+				phy-mode = "2500base-x";
+			};
+		};
+	};
+};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso

@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
+
+	fragment@0 {
+		target = <&spi0>;
+		__overlay__ {
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			spi_nand: spi_nand@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				reg = <1>;
+				spi-max-frequency = <10000000>;
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+
+				partitions {
+					compatible = "fixed-partitions";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					partition@0 {
+						label = "BL2";
+						reg = <0x00000 0x0100000>;
+						read-only;
+					};
+
+					partition@100000 {
+						label = "u-boot-env";
+						reg = <0x0100000 0x0080000>;
+					};
+
+					factory: partition@180000 {
+						label = "Factory";
+						reg = <0x180000 0x0200000>;
+					};
+
+					partition@380000 {
+						label = "FIP";
+						reg = <0x380000 0x0200000>;
+					};
+
+					partition@580000 {
+						label = "ubi";
+						reg = <0x580000 0x4000000>;
+					};
+				};
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&wifi>;
+		__overlay__ {
+			mediatek,mtd-eeprom = <&factory 0x0>;
+			status = "okay";
+		};
+	};
+};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts

@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <[email protected]>
+ */
+
+/dts-v1/;
+#include "mt7981.dtsi"
+
+/ {
+	model = "MediaTek MT7981 RFB";
+	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		reg = <0 0x40000000 0 0x20000000>;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_5v: regulator-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		reset {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+		};
+		wps {
+			label = "wps";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&eth {
+	status = "okay";
+
+	gmac0: mac@0 {
+		compatible = "mediatek,eth-mac";
+		reg = <0>;
+		phy-mode = "2500base-x";
+
+		fixed-link {
+			speed = <2500>;
+			full-duplex;
+			pause;
+		};
+	};
+
+	gmac1: mac@1 {
+		compatible = "mediatek,eth-mac";
+		reg = <1>;
+		phy-mode = "gmii";
+		phy-handle = <&int_gbe_phy>;
+	};
+};
+
+&mdio_bus {
+	switch: switch@1f {
+		compatible = "mediatek,mt7531";
+		reg = <31>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		interrupt-parent = <&pio>;
+		interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&crypto {
+	status = "okay";
+};
+
+&pio {
+	spi0_flash_pins: spi0-pins {
+		mux {
+			function = "spi";
+			groups = "spi0", "spi0_wp_hold";
+		};
+		conf-pu {
+			pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+		};
+		conf-pd {
+			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+		};
+	};
+
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_flash_pins>;
+	cs-gpios = <0>, <0>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "disabled";
+};
+
+&switch {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			label = "lan1";
+		};
+
+		port@1 {
+			reg = <1>;
+			label = "lan2";
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan3";
+		};
+
+		port@3 {
+			reg = <3>;
+			label = "lan4";
+		};
+
+		sw_p5: port@5 {
+			reg = <5>;
+			label = "lan5";
+			status = "disabled";
+		};
+
+		port@6 {
+			reg = <6>;
+			ethernet = <&gmac0>;
+			phy-mode = "2500base-x";
+
+			fixed-link {
+				speed = <2500>;
+				full-duplex;
+				pause;
+			};
+		};
+	};
+};
+
+&xhci {
+	vusb33-supply = <&reg_3p3v>;
+	vbus-supply = <&reg_5v>;
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usb_phy {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};

target/linux/mediatek/filogic/base-files/etc/board.d/02_network

@@ -11,7 +11,8 @@ mediatek_setup_interfaces()
 	acer,predator-w6)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 game" eth1
 		;;
-	asus,tuf-ax4200)
+	asus,tuf-ax4200|\
+	mediatek,mt7981-rfb)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1
 		;;
 	netgear,wax220|\

target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh

@@ -89,6 +89,7 @@ platform_do_upgrade() {
 		nand_do_upgrade "$1"
 		;;
 	h3c,magic-nx30-pro|\
+	mediatek,mt7981-rfb|\
 	qihoo,360t7|\
 	tplink,tl-xdr4288|\
 	tplink,tl-xdr6086|\