Use alternate chip reset for updates

The standard ARM system reset will not reset certain hardware blocks,
notably the flash lock registers for the protected flash regions.
Use the alternate syscon reset to ensure we can write our CFPA updates.

drv/lpc55-syscon/src/main.rs

@@ -195,6 +195,17 @@ impl idl::InOrderSysconImpl for ServerImpl<'_> {
 
         Ok(())
     }
+
+    fn chip_reset(
+        &mut self,
+        _: &RecvMessage,
+    ) -> Result<(), RequestError<core::convert::Infallible>> {
+        // Documented in 4.5.16 Software reset register of UM11126
+        self.syscon
+            .swr_reset
+            .write(|w| unsafe { w.swr_reset().bits(0x5a00_0001) });
+        panic!();
+    }
 }
 
 #[export_name = "main"]
@@ -219,7 +230,13 @@ fn main() -> ! {
     // turning on PLLs and such
     syscon.hslspiclksel.modify(|_, w| w.sel().enum_0x2());
 
-    set_reset_reason();
+    let pmc = unsafe { &*device::PMC::ptr() };
+
+    // Need this to be able to use the syscon reset that works for CFPA
+    // update
+    pmc.resetctrl.write(|w| w.swrresetenable().enable());
+
+    set_reset_reason(pmc);
 
     let mut server = ServerImpl { syscon };
 
@@ -229,9 +246,7 @@ fn main() -> ! {
     }
 }
 
-fn set_reset_reason() {
-    let pmc = unsafe { &*device::PMC::ptr() };
-
+fn set_reset_reason(pmc: &device::pmc::RegisterBlock) {
     // The Reset Reason is stored in the AOREG1 register in the power
     // management block. This crypticly named register is set based
     // on another undocumented register in the power management space.

drv/lpc55-update-server/src/main.rs

@@ -422,7 +422,7 @@ impl idl::InOrderUpdateImpl for ServerImpl<'_> {
         if self.state == UpdateState::InProgress {
             return Err(UpdateError::UpdateInProgress.into());
         }
-        task_jefe_api::Jefe::from(JEFE.get_task_id()).request_reset();
+        self.syscon.chip_reset();
         panic!()
     }
 }

idl/syscon.idol

@@ -29,5 +29,10 @@ Interface(
 		reply: Simple("()"),
 		idempotent: true,
 	),
+	"chip_reset": (
+		reply: Simple("()"),
+		idempotent: true,
+	),
+
    }
 )