I wrote this Verilog IP to accelerate chirp estimation using the Fractional Fourier Transform algorithm on an Altera FPGA device.
Chirp estimation is commonly used on both stationary and airborne radar equipment to determine both the speed and trajectory of moving objects on a 3D coordinate space. If you're interested in the math involved, see more here: https://e-reports-ext.llnl.gov/pdf/830491.pdf
The research behind this project has also been published in an IEEE journal: https://ieeexplore.ieee.org/document/5929841
This repo is mostly for historical and reference purposes since it hasn't been touched in 10 years. I ran it on an Altera DE2 board (which is discontinued so they don't even sell it anymore) but it should run on any FPGA with enough gates.
Feel free to browse the repo -- especially if you're an FPGA beginner. There are some parts I did really well and there are others that I'd done.. not so well. As said, for reference only.
This repo is published as-is, which means the author takes no responsibility whatsoever. Building this into a bitstream file and loading it on an FPGA could result in anything ranging from your house catching fire, to random military aircraft acquiring missile lock on you. Be wary.
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