Skip to content

Commit

Permalink
Actually do something with delay asymmetry.
Browse files Browse the repository at this point in the history
  • Loading branch information
davidv1992 authored and rnijveld committed Nov 30, 2023
1 parent cae1903 commit 3c8f82a
Show file tree
Hide file tree
Showing 3 changed files with 130 additions and 25 deletions.
12 changes: 8 additions & 4 deletions statime/src/port/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -399,6 +399,7 @@ impl<'a, A: AcceptableMasterList, C: Clock, F: Filter, R: Rng> Port<Running<'a>,
timestamp: Time,
) -> PortActionIterator<'_> {
let actions = self.port_state.handle_timestamp(
self.config.delay_asymmetry,
context,
timestamp,
self.port_identity,
Expand Down Expand Up @@ -505,6 +506,7 @@ impl<'a, A: AcceptableMasterList, C: Clock, F: Filter, R: Rng> Port<Running<'a>,

if message.is_event() {
self.port_state.handle_event_receive(
self.config.delay_asymmetry,
message,
timestamp,
self.config.min_delay_req_interval(),
Expand Down Expand Up @@ -551,10 +553,12 @@ impl<'a, A: AcceptableMasterList, C: Clock, F: Filter, R: Rng> Port<Running<'a>,
actions![]
}
}
_ => {
self.port_state
.handle_general_receive(message, self.port_identity, &mut self.clock)
}
_ => self.port_state.handle_general_receive(
self.config.delay_asymmetry,
message,
self.port_identity,
&mut self.clock,
),
}
}
}
Expand Down
19 changes: 15 additions & 4 deletions statime/src/port/state/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ use crate::{
datastructures::{common::PortIdentity, datasets::DefaultDS, messages::Message},
filters::Filter,
ptp_instance::PtpInstanceState,
time::{Interval, Time},
time::{Duration, Interval, Time},
Clock,
};

Expand All @@ -28,8 +28,10 @@ pub(crate) enum PortState<F> {
}

impl<F: Filter> PortState<F> {
#[allow(clippy::too_many_arguments)]
pub(crate) fn handle_timestamp<'a, C: Clock>(
&mut self,
delay_asymmetry: Duration,
context: TimestampContext,
timestamp: Time,
port_identity: PortIdentity,
Expand All @@ -38,16 +40,20 @@ impl<F: Filter> PortState<F> {
buffer: &'a mut [u8],
) -> PortActionIterator<'a> {
match self {
PortState::Slave(slave) => slave.handle_timestamp(context, timestamp, clock),
PortState::Slave(slave) => {
slave.handle_timestamp(delay_asymmetry, context, timestamp, clock)
}
PortState::Master(master) => {
master.handle_timestamp(context, timestamp, port_identity, default_ds, buffer)
}
PortState::Listening | PortState::Passive => actions![],
}
}

#[allow(clippy::too_many_arguments)]
pub(crate) fn handle_event_receive<'a, C: Clock>(
&mut self,
delay_asymmetry: Duration,
message: Message,
timestamp: Time,
min_delay_req_interval: Interval,
Expand All @@ -63,13 +69,16 @@ impl<F: Filter> PortState<F> {
port_identity,
buffer,
),
PortState::Slave(slave) => slave.handle_event_receive(message, timestamp, clock),
PortState::Slave(slave) => {
slave.handle_event_receive(delay_asymmetry, message, timestamp, clock)
}
PortState::Listening | PortState::Passive => actions![],
}
}

pub(crate) fn handle_general_receive<C: Clock>(
&mut self,
delay_asymmetry: Duration,
message: Message,
port_identity: PortIdentity,
clock: &mut C,
Expand All @@ -81,7 +90,9 @@ impl<F: Filter> PortState<F> {
}
actions![]
}
PortState::Slave(slave) => slave.handle_general_receive(message, port_identity, clock),
PortState::Slave(slave) => {
slave.handle_general_receive(delay_asymmetry, message, port_identity, clock)
}
PortState::Listening | PortState::Passive => {
actions![]
}
Expand Down
Loading

0 comments on commit 3c8f82a

Please sign in to comment.