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windows program fix and easy compile, patch and run example script #25

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windows program fix and easy compile, patch and run example script #25

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ca7ff82
try fixing windows scripts
onsdagens Aug 22, 2024
a01d850
added script for easy compiling, patching and programming examples
Mehdows Sep 9, 2024
182ff1e
removed accidental dupe of run.cmd
Mehdows Sep 9, 2024
70a69b0
stack isolation complete with blocking memory access above and below …
Mehdows Sep 10, 2024
0991c07
Merge branch 'stack_isolation'
Mehdows Sep 10, 2024
fdf677a
added a register for each entry pointer
Mehdows Sep 16, 2024
6726bae
removed register and added latches for ep storing. also changed ep up…
Mehdows Sep 17, 2024
c4e29cd
backup
Mehdows Sep 23, 2024
9b18258
refactor
Mehdows Sep 26, 2024
b7abeff
test
Mehdows Oct 10, 2024
55bfb10
rework
Mehdows Oct 10, 2024
db4fce1
added pmp and such to project
Mehdows Oct 10, 2024
e7633de
Merge branch 'master' of https://github.com/Mehdows/hippomenes
Mehdows Oct 10, 2024
fbf68f3
test
Mehdows Oct 10, 2024
433cb47
test
Mehdows Oct 11, 2024
e6928f2
Merge branch 'master' of https://github.com/Mehdows/hippomenes
Mehdows Oct 11, 2024
43b06e0
reworked pmp
Mehdows Oct 15, 2024
7ff3491
fixed potential comb blocking
Mehdows Oct 16, 2024
74a7351
fixed everything
Mehdows Oct 16, 2024
eac9cdc
Merge branch 'master' into test
Mehdows Oct 16, 2024
6cbcbe6
sMerge branch 'master' of https://github.com/Mehdows/hippomenes
Mehdows Oct 17, 2024
324ec73
wrote tests for all mpu scenarios and fixed small flaws in the mpu
Mehdows Oct 18, 2024
be04fed
did some changes and fixed serial output for tests
Mehdows Nov 6, 2024
c88827a
Merge https://github.com/perlindgren/hippomenes
Mehdows Nov 6, 2024
2c01729
updated examples for ncobs
Mehdows Nov 6, 2024
207c19f
yes
Mehdows Nov 8, 2024
352af87
it should work now
Mehdows Nov 11, 2024
caadcdb
fix
Mehdows Nov 11, 2024
0627582
changed csr format and fixed mpu
Mehdows Nov 15, 2024
9611690
pmp should work now for realz, also changed csr layout for pmp and am…
Mehdows Nov 16, 2024
5c3b821
hm
Mehdows Nov 18, 2024
0dce0ce
test
Mehdows Nov 18, 2024
0d35d6e
fix id out
onsdagens Nov 18, 2024
cd464de
not synthable
Mehdows Nov 19, 2024
2cb769c
fixed nclic int_id
Mehdows Nov 20, 2024
bef5110
n_clic return id is now not delayed one cycle
Mehdows Nov 20, 2024
a6be2c7
mpu works but is delayed
Mehdows Nov 20, 2024
12079b4
working version, ep_vec is now correctly updated when memex happens
Mehdows Nov 21, 2024
d51e4a7
csr_block complete
Mehdows Nov 22, 2024
47c7914
csr_block complete, with the actual files getting commited
Mehdows Nov 22, 2024
cc032b1
added a fix for when the csr list is full so it doesn't loop
Mehdows Jan 20, 2025
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9 changes: 9 additions & 0 deletions fpga/.Xil/Vivado-16040-MarcusDator/.lpr
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Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->

<labtools version="1" minor="0">
<HWSession Dir="hw_1" File="hw.xml"/>
</labtools>
30 changes: 30 additions & 0 deletions fpga/arty.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -138,6 +138,8 @@ proc checkRequiredFiles { origin_dir} {
"[file normalize "$origin_dir/../rust_examples/data_1.mem"]"\
"[file normalize "$origin_dir/arty_top/arty.srcs/constrs_1/new/ARTY.xdc"]"\
"[file normalize "$origin_dir/../hdl/src/tb_top_arty.sv"]"\
"[file normalize "$origin_dir/../hdl/src/core/mpu.sv"]"\
"[file normalize "$origin_dir/../hdl/src/core/csr_block.sv"]"\
]
foreach ifile $files {
if { ![file isfile $ifile] } {
Expand Down Expand Up @@ -367,6 +369,8 @@ set files [list \
[file normalize "${origin_dir}/../rust_examples/data_2.mem"] \
[file normalize "${origin_dir}/../rust_examples/data_0.mem"] \
[file normalize "${origin_dir}/../rust_examples/data_1.mem"] \
[file normalize "${origin_dir}/../hdl/src/core/mpu.sv"] \
[file normalize "${origin_dir}/../hdl/src/core/csr_block.sv"] \
]
add_files -norecurse -fileset $obj $files

Expand Down Expand Up @@ -959,6 +963,32 @@ set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj


set file "$origin_dir/../hdl/src/core/mpu.sv"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
set_property -name "used_in_implementation" -value "1" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj


set file "$origin_dir/../hdl/src/core/csr_block.sv"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
set_property -name "used_in_implementation" -value "1" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
# Set 'sources_1' fileset file properties for local files
# None

Expand Down
38 changes: 19 additions & 19 deletions fpga/arty_top/arty.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
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Original file line number Diff line number Diff line change
Expand Up @@ -84,7 +84,7 @@
"PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
"PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
"PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "20.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
Expand Down Expand Up @@ -154,9 +154,9 @@
"SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
"OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
"MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MMCM_DIVCLK_DIVIDE": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
"MMCM_CLKFBOUT_MULT_F": [ { "value": "8.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKFBOUT_MULT_F": [ { "value": "15.625", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
Expand All @@ -167,7 +167,7 @@
"MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "42.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "78.125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
Expand Down Expand Up @@ -245,8 +245,8 @@
"CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
"ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT1_JITTER": [ { "value": "193.154", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT1_PHASE_ERROR": [ { "value": "109.126", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT1_JITTER": [ { "value": "290.478", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT1_PHASE_ERROR": [ { "value": "133.882", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT2_JITTER": [ { "value": "281.382", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT2_PHASE_ERROR": [ { "value": "301.601", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
Expand Down Expand Up @@ -338,14 +338,14 @@
"C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__20.00000______0.000______50.0______193.154____109.126", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__10.00000______0.000______50.0______290.478____133.882", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW2": [ { "value": "no_CLK_OUT2_output", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "20.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
Expand All @@ -366,7 +366,7 @@
"C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_CLKOUT1_OUT_FREQ": [ { "value": "20.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_CLKOUT1_OUT_FREQ": [ { "value": "10.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_CLKOUT2_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
Expand Down Expand Up @@ -398,17 +398,17 @@
"C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
"C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "8.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "15.625", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "42.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "78.125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
Expand Down Expand Up @@ -540,12 +540,12 @@
"C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
"C_DIVIDE2_AUTO": [ { "value": "0.023529411764705882", "resolve_type": "generated", "usage": "all" } ],
"C_DIVIDE3_AUTO": [ { "value": "0.023529411764705882", "resolve_type": "generated", "usage": "all" } ],
"C_DIVIDE4_AUTO": [ { "value": "0.023529411764705882", "resolve_type": "generated", "usage": "all" } ],
"C_DIVIDE5_AUTO": [ { "value": "0.023529411764705882", "resolve_type": "generated", "usage": "all" } ],
"C_DIVIDE6_AUTO": [ { "value": "0.023529411764705882", "resolve_type": "generated", "usage": "all" } ],
"C_DIVIDE7_AUTO": [ { "value": "0.023529411764705882", "resolve_type": "generated", "usage": "all" } ],
"C_DIVIDE2_AUTO": [ { "value": "0.0128", "resolve_type": "generated", "usage": "all" } ],
"C_DIVIDE3_AUTO": [ { "value": "0.0128", "resolve_type": "generated", "usage": "all" } ],
"C_DIVIDE4_AUTO": [ { "value": "0.0128", "resolve_type": "generated", "usage": "all" } ],
"C_DIVIDE5_AUTO": [ { "value": "0.0128", "resolve_type": "generated", "usage": "all" } ],
"C_DIVIDE6_AUTO": [ { "value": "0.0128", "resolve_type": "generated", "usage": "all" } ],
"C_DIVIDE7_AUTO": [ { "value": "0.0128", "resolve_type": "generated", "usage": "all" } ],
"C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
"C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
"C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
Expand All @@ -566,7 +566,7 @@
"C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "20.00000", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "10.00000", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT1_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
Expand Down
3 changes: 1 addition & 2 deletions fpga/program_arty.cmd
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@@ -1,3 +1,2 @@
call updatemem --meminfo arty/arty.runs/impl_1/fpga_arty.mmi --data ../rust_examples/binary.mem --proc hippo/imem/xpm_memory_spram_inst/xpm_memory_base_inst --bit arty/arty.runs/impl_1/fpga_arty.bit -out arty/arty.runs/impl_1/fpga_arty.bit -force
call updatemem --bit arty/arty.runs/impl_1/fpga_arty.bit --meminfo arty/arty.runs/impl_1/fpga_arty.mmi --data ../rust_examples/text.mem --proc hippo/imem/xpm_memory_spram_inst/xpm_memory_base_inst --data ../rust_examples/data_0.mem --proc hippo/dmem/block_0/xpm_memory_spram_inst/xpm_memory_base_inst --data ../rust_examples/data_1.mem --proc hippo/dmem/block_1/xpm_memory_spram_inst/xpm_memory_base_inst --data ../rust_examples/data_2.mem --proc hippo/dmem/block_2/xpm_memory_spram_inst/xpm_memory_base_inst --data ../rust_examples/data_3.mem --proc hippo/dmem/block_3/xpm_memory_spram_inst/xpm_memory_base_inst -out arty/arty.runs/impl_1/fpga_arty.bit -force
call vivado -mode tcl -source program_arty.tcl

9 changes: 9 additions & 0 deletions fpga/run.cmd
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@@ -0,0 +1,9 @@
:: Just do "run.cmd your_rust_program_here"
echo off
set arg1=%1
cd ..\rust_examples\
cargo build --example %1 --release
if %errorlevel% neq 0 exit /b %errorlevel%
elf2mem -f ./target/riscv32i-unknown-none-elf/release/examples/%1
cd ..\fpga
program_arty.cmd
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