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Update COREAXI4DMACONTROLLER and LSRAM version
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Updated COREAXI4DMACONTROLLER from version 2.0.100 to version 2.2.107
for simulations to work in QuestaSim, and modified the bus interface net
name connections in the script to accommodate the Initiator/Target
convention.

Updated PF_SRAM_AHBL_AXI instance generation to use * instead of version
number as it is a non-direct core.

Signed-off-by: Brian Burke <[email protected]>
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Brian Burke authored and Brian Burke committed Sep 12, 2024
1 parent 61c4ba9 commit 7ab8119
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Showing 5 changed files with 8 additions and 8 deletions.
2 changes: 1 addition & 1 deletion MPFS_ICICLE_KIT_REFERENCE_DESIGN.tcl
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Expand Up @@ -150,7 +150,7 @@ if { [file exists $project_dir/$project_name.prjx] } {
download_core -vlnv {Actel:SgCore:PF_TX_PLL:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_XCVR_REF_CLK:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREAXI4DMACONTROLLER:2.0.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREAXI4DMACONTROLLER:2.2.107} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:SystemBuilder:PF_SRAM_AHBL_AXI:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:Simulation:CLK_GEN:*} -location {www.microchip-ip.com/repositories/SgCore}
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2 changes: 1 addition & 1 deletion ...pport/additional_configurations/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR.tcl
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Expand Up @@ -12,7 +12,7 @@ open_smartdesign -sd_name {FIC_0_PERIPHERALS}

# updating the dma controller to the latest version
sd_update_instance -sd_name {FIC_0_PERIPHERALS} -instance_name {DMA_CONTROLLER}
update_component_version -component_name {DMA_CONTROLLER} -new_version {2.1.102} -download_core
update_component_version -component_name {DMA_CONTROLLER} -new_version {*} -download_core

# configuring the dma controller to include the axi stream inputs
configure_core -component_name {DMA_CONTROLLER} -params {"AXI4_STREAM_IF:true" "AXI_DMA_DWIDTH:64" "DSCRPTR_0_INT_ASSOC:0" "DSCRPTR_0_PRI_LVL:0" "DSCRPTR_10_INT_ASSOC:0" "DSCRPTR_10_PRI_LVL:0" "DSCRPTR_11_INT_ASSOC:0" "DSCRPTR_11_PRI_LVL:0" "DSCRPTR_12_INT_ASSOC:0" "DSCRPTR_12_PRI_LVL:0" "DSCRPTR_13_INT_ASSOC:0" "DSCRPTR_13_PRI_LVL:0" "DSCRPTR_14_INT_ASSOC:0" "DSCRPTR_14_PRI_LVL:0" "DSCRPTR_15_INT_ASSOC:0" "DSCRPTR_15_PRI_LVL:0" "DSCRPTR_16_INT_ASSOC:0" "DSCRPTR_16_PRI_LVL:0" "DSCRPTR_17_INT_ASSOC:0" "DSCRPTR_17_PRI_LVL:0" "DSCRPTR_18_INT_ASSOC:0" "DSCRPTR_18_PRI_LVL:0" "DSCRPTR_19_INT_ASSOC:0" "DSCRPTR_19_PRI_LVL:0" "DSCRPTR_1_INT_ASSOC:0" "DSCRPTR_1_PRI_LVL:0" "DSCRPTR_20_INT_ASSOC:0" "DSCRPTR_20_PRI_LVL:0" "DSCRPTR_21_INT_ASSOC:0" "DSCRPTR_21_PRI_LVL:0" "DSCRPTR_22_INT_ASSOC:0" "DSCRPTR_22_PRI_LVL:0" "DSCRPTR_23_INT_ASSOC:0" "DSCRPTR_23_PRI_LVL:0" "DSCRPTR_24_INT_ASSOC:0" "DSCRPTR_24_PRI_LVL:0" "DSCRPTR_25_INT_ASSOC:0" "DSCRPTR_25_PRI_LVL:0" "DSCRPTR_26_INT_ASSOC:0" "DSCRPTR_26_PRI_LVL:0" "DSCRPTR_27_INT_ASSOC:0" "DSCRPTR_27_PRI_LVL:0" "DSCRPTR_28_INT_ASSOC:0" "DSCRPTR_28_PRI_LVL:0" "DSCRPTR_29_INT_ASSOC:0" "DSCRPTR_29_PRI_LVL:0" "DSCRPTR_2_INT_ASSOC:0" "DSCRPTR_2_PRI_LVL:0" "DSCRPTR_30_INT_ASSOC:0" "DSCRPTR_30_PRI_LVL:0" "DSCRPTR_31_INT_ASSOC:0" "DSCRPTR_31_PRI_LVL:0" "DSCRPTR_3_INT_ASSOC:0" "DSCRPTR_3_PRI_LVL:0" "DSCRPTR_4_INT_ASSOC:0" "DSCRPTR_4_PRI_LVL:0" "DSCRPTR_5_INT_ASSOC:0" "DSCRPTR_5_PRI_LVL:0" "DSCRPTR_6_INT_ASSOC:0" "DSCRPTR_6_PRI_LVL:0" "DSCRPTR_7_INT_ASSOC:0" "DSCRPTR_7_PRI_LVL:0" "DSCRPTR_8_INT_ASSOC:0" "DSCRPTR_8_PRI_LVL:0" "DSCRPTR_9_INT_ASSOC:0" "DSCRPTR_9_PRI_LVL:0" "ECC:false" "ID_WIDTH:8" "INT_0_QUEUE_DEPTH:1" "INT_1_QUEUE_DEPTH:1" "INT_2_QUEUE_DEPTH:1" "INT_3_QUEUE_DEPTH:1" "NUM_INT_BDS:4" "NUM_OF_INTS:4" "NUM_PRI_LVLS:1" "PRI_0_NUM_OF_BEATS:256" "PRI_1_NUM_OF_BEATS:128" "PRI_2_NUM_OF_BEATS:64" "PRI_3_NUM_OF_BEATS:32" "PRI_4_NUM_OF_BEATS:16" "PRI_5_NUM_OF_BEATS:8" "PRI_6_NUM_OF_BEATS:4" "PRI_7_NUM_OF_BEATS:1"}
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4 changes: 2 additions & 2 deletions ...t/additional_configurations/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR_BFM.tcl
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Expand Up @@ -11,7 +11,7 @@ import_files \

open_smartdesign -sd_name {FIC_0_PERIPHERALS}
sd_update_instance -sd_name {FIC_0_PERIPHERALS} -instance_name {DMA_CONTROLLER}
update_component_version -component_name {DMA_CONTROLLER} -new_version {2.1.102} -download_core
update_component_version -component_name {DMA_CONTROLLER} -new_version {*} -download_core

puts " =============updated DMA controller to latest version"

Expand Down Expand Up @@ -64,7 +64,7 @@ sd_connect_pins -sd_name {FIC_0_PERIPHERALS} -pin_names {"ARESETN" "COREAXI4INTE

puts " =============Instantiate the SRAM"
# Instantiate the SRAM
create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_SRAM_AHBL_AXI:1.2.110} -component_name {PF_SRAM_AHBL_AXI_C0} -params {"AXI4_AWIDTH:32" "AXI4_DWIDTH:64" "AXI4_IDWIDTH:8" "AXI4_IFTYPE_RD:T" "AXI4_IFTYPE_WR:T" "AXI4_WRAP_SUPPORT:F" "BYTEENABLES:1" "BYTE_ENABLE_WIDTH:8" "B_REN_POLARITY:2" "CASCADE:1" "ECC_OPTIONS:0" "FABRIC_INTERFACE_TYPE:1" "IMPORT_FILE:" "INIT_RAM:F" "LPM_HINT:0" "PIPELINE_OPTIONS:1" "RDEPTH:2048" "RWIDTH:80" "USE_NATIVE_INTERFACE:F" "WDEPTH:2048" "WWIDTH:80"}
create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_SRAM_AHBL_AXI:*} -component_name {PF_SRAM_AHBL_AXI_C0} -params {"AXI4_AWIDTH:32" "AXI4_DWIDTH:64" "AXI4_IDWIDTH:8" "AXI4_IFTYPE_RD:T" "AXI4_IFTYPE_WR:T" "AXI4_WRAP_SUPPORT:F" "BYTEENABLES:1" "BYTE_ENABLE_WIDTH:8" "B_REN_POLARITY:2" "CASCADE:1" "ECC_OPTIONS:0" "FABRIC_INTERFACE_TYPE:1" "IMPORT_FILE:" "INIT_RAM:F" "LPM_HINT:0" "PIPELINE_OPTIONS:1" "RDEPTH:2048" "RWIDTH:80" "USE_NATIVE_INTERFACE:F" "WDEPTH:2048" "WWIDTH:80"}
sd_instantiate_component -sd_name {FIC_0_PERIPHERALS} -component_name {PF_SRAM_AHBL_AXI_C0} -instance_name {}
sd_connect_pins -sd_name {FIC_0_PERIPHERALS} -pin_names {"ACLK" "PF_SRAM_AHBL_AXI_C0_0:ACLK"}
sd_connect_pins -sd_name {FIC_0_PERIPHERALS} -pin_names {"ARESETN" "PF_SRAM_AHBL_AXI_C0_0:ARESETN"}
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2 changes: 1 addition & 1 deletion script_support/components/DMA_CONTROLLER.tcl
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Expand Up @@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS250T_ES-FCVG484E
# Create and Configure the core component DMA_CONTROLLER
create_and_configure_core -core_vlnv {Actel:DirectCore:COREAXI4DMACONTROLLER:2.0.100} -component_name {DMA_CONTROLLER} -params {\
create_and_configure_core -core_vlnv {Actel:DirectCore:COREAXI4DMACONTROLLER:2.2.107} -component_name {DMA_CONTROLLER} -params {\
"AXI4_STREAM_IF:false" \
"AXI_DMA_DWIDTH:32" \
"DSCRPTR_0_INT_ASSOC:0" \
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6 changes: 3 additions & 3 deletions script_support/components/FIC_0_PERIPHERALS.tcl
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Expand Up @@ -228,9 +228,9 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"DMA_CONTROLLER:INTERRUPT[0:0]"
# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4mmaster0" "FIC0_INITIATOR:AXI4mmaster0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4mslave0" "DMA_INITIATOR:AXI4mslave0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DMA_CONTROLLER:AXI4MasterDMA_IF" "DMA_INITIATOR:AXI4mmaster0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DMA_CONTROLLER:AXI4SlaveCtrl_IF" "FIC0_INITIATOR:AXI4mslave0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FIC0_INITIATOR:AXI4mslave1" "MSS_LSRAM:AXI4_Slave" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DMA_CONTROLLER:AXI4InitiatorDMA_IF" "DMA_INITIATOR:AXI4mmaster0"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"DMA_CONTROLLER:AXI4TargetCtrl_IF" "FIC0_INITIATOR:AXI4mslave0"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"FIC0_INITIATOR:AXI4mslave1" "MSS_LSRAM:AXI4_Slave"}

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
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