ignore delay statements in processes

.gitignore

@@ -0,0 +1,3 @@
+/build/
+.*
+!/.git*

src/initial_eval.cc

@@ -42,8 +42,9 @@ inline constexpr slang::DiagCode ParallelBlockUnsupported(DiagSubsystem::Netlist
 inline constexpr slang::DiagCode TODO(DiagSubsystem::Netlist, 102);
 inline constexpr slang::DiagCode BadEvaluation(DiagSubsystem::Netlist, 103);
 
-EvalVisitor::EvalVisitor(Compilation *compilation)
+EvalVisitor::EvalVisitor(Compilation *compilation, bool ignore_timing)
 	: context(ASTContext(compilation->getRoot(), LookupLocation::max), /* HACK */ ast::EvalFlags::IsScript)
+	, ignore_timing(ignore_timing)
 {
 	context.pushEmptyFrame();
 }
@@ -684,6 +685,16 @@ ER EvalVisitor::visit(const ImmediateAssertionStatement &stmt)
 	return ER::Success;
 }
 
+ER EvalVisitor::visit(const TimedStatement &stmt)
+{
+	if (!ignore_timing) // call unimplemented
+		return visit(static_cast<const Statement &>(stmt));
+
+	// ignore timing and visit inner statement
+	ER result = stmt.stmt.visit(*this);
+	return result;
+}
+
 ER EvalVisitor::visit(const EmptyStatement&)
 {
 	return ER::Success;

src/initial_eval.h

@@ -6,7 +6,7 @@ namespace SlangInitial {
 struct EvalVisitor {
 public:
 	slang::ast::EvalContext context;
-	EvalVisitor(slang::ast::Compilation *compilation);
+	EvalVisitor(slang::ast::Compilation *compilation, bool ignore_timing = false);
 
 	using ER = slang::ast::Statement::EvalResult;
 
@@ -33,11 +33,14 @@ struct EvalVisitor {
 	ER visit(const slang::ast::ForeverLoopStatement &stmt);
 	ER visit(const slang::ast::ExpressionStatement &stmt);
 	ER visit(const slang::ast::ImmediateAssertionStatement &stmt);
+	ER visit(const slang::ast::TimedStatement &stmt);
 	ER visit(const slang::ast::EmptyStatement &stmt);
 	ER visit(const slang::ast::Statement &);
 
 	// to let clients choose the display handling
 	virtual void handleDisplay(const slang::ast::CallExpression &call,
 							   const std::vector<slang::ConstantValue> &args);
+
+	bool ignore_timing;
 };
 };

src/slang_frontend.cc

@@ -36,6 +36,7 @@ struct SynthesisSettings {
 	std::optional<bool> compat_mode;
 	std::optional<bool> keep_hierarchy;
 	std::optional<bool> best_effort_hierarchy;
+	std::optional<bool> ignore_timing;
 
 	enum HierMode {
 		NONE,
@@ -61,6 +62,8 @@ struct SynthesisSettings {
 					"Keep hierarchy (experimental; may crash)");
 		cmdLine.add("--best-effort-hierarchy", best_effort_hierarchy,
 					"Keep hierarchy in a 'best effort' mode");
+		cmdLine.add("--ignore-timing", ignore_timing,
+		            "Ignore delays for synthesis");
 	}
 };
 
@@ -1236,6 +1239,14 @@ struct ProceduralVisitor : public ast::ASTVisitor<ProceduralVisitor, true, false
 		}
 	}
 
+	void handle(const ast::TimedStatement &stmt)
+	{
+		if (netlist.settings.ignore_timing.value_or(false))
+			stmt.stmt.visit(*this);
+		else
+			unimplemented(stmt);
+	}
+
 	void handle(const ast::Statement &stmt)
 	{
 		unimplemented(stmt);
@@ -1854,8 +1865,8 @@ struct PopulateNetlist : public TimingPatternInterpretor, public ast::ASTVisitor
 		RTLIL::Module *mod;
 		int print_priority;
 
-		InitialEvalVisitor(ast::Compilation *compilation, RTLIL::Module *mod)
-			: SlangInitial::EvalVisitor(compilation), mod(mod), print_priority(0) {}
+		InitialEvalVisitor(ast::Compilation *compilation, RTLIL::Module *mod, bool ignore_timing=false)
+			: SlangInitial::EvalVisitor(compilation, ignore_timing), mod(mod), print_priority(0) {}
 
 		void handleDisplay(const slang::ast::CallExpression &call, const std::vector<slang::ConstantValue> &args) {
 			auto cell = mod->addCell(NEW_ID, ID($print));
@@ -1899,7 +1910,7 @@ struct PopulateNetlist : public TimingPatternInterpretor, public ast::ASTVisitor
 	} initial_eval;
 
 	PopulateNetlist(NetlistContext &netlist)
-		: netlist(netlist), settings(netlist.settings), initial_eval(&netlist.compilation, netlist.canvas) {}
+		: netlist(netlist), settings(netlist.settings), initial_eval(&netlist.compilation, netlist.canvas, netlist.settings.ignore_timing.value_or(false)) {}
 
 	void handle_comb_like_process(const ast::ProceduralBlockSymbol &symbol, const ast::Statement &body)
 	{

tests/various/delays.sv

@@ -0,0 +1,44 @@
+`timescale 1ns/1ps
+
+module top(input wire clk);
+
+wire #10 a;
+wire #(10+0) b;
+wire #(10+0, 1+1) c;
+wire #(10+0, 1+1, 2+2) d;
+
+assign #10 a = b;
+assign #(10+1) b = c;
+
+reg ra, rb;
+always @(posedge clk) begin
+    #1;
+    #1 ra <= a;
+    rb <= #1 a;
+end
+
+logic la, lb;
+always @(*) begin
+    #10;
+    #10 la = a;
+    lb = #10 a;
+end
+
+logic lc, ld;
+initial begin
+    #10;
+    #10 lc = ra;
+    ld = #10 ra;
+end
+
+int foo;
+
+initial begin
+    #10 foo = 32'h0;
+    $display(foo);
+    #10 foo = 32'hdeadbeef;
+    $display(foo);
+end
+
+
+endmodule

tests/various/delays.ys

@@ -0,0 +1 @@
+read_slang --ignore-timing delays.sv