Enforce linear buffer for decoding in the case of hybrid-GPU

In hybrid GPU case, video decoder could be iGPU and the coded images
would be consumed by dGPU. Unfortunately, it's likely that we can hardly
find a tiling format supported by both of them. To achieve best
compatibility and make our life better, simply use linear buffers for
decoded images.

By setting CPU_READ and CPU_WRITE flags, we force OneVPL to allocate
internal buffers and blit decoded content to external buffers. In this
way we can work around hardware limitation that DG2 cannot decode to
linear buffers.

We will detect the GPU group type and decide whether to use linear
buffers or not.

Tracked-On: OAM-126399
Signed-off-by: Weifeng Liu <weifeng.liu@intel.com>

c2_components/include/mfx_c2_decoder_component.h

@@ -28,6 +28,7 @@
 #include "mfx_c2_bitstream_in.h"
 #include "mfx_frame_pool_allocator.h"
 #include "mfx_gralloc_instance.h"
+#include "mfx_intel_device.h"
 #include "mfx_c2_setters.h"
 #include "mfx_c2_utils.h"
 #include <cutils/properties.h>
@@ -264,6 +265,7 @@ class MfxC2DecoderComponent : public MfxC2Component
     // dump output multiple times, the first dumped file named xxx_0.yuv,
     // second dumped file named xxx_1.yuv ...
     uint32_t m_file_num = 0;
+    bool m_needCpuAccess = false;
 
     /* -----------------------C2Parameters--------------------------- */
     std::shared_ptr<C2ComponentNameSetting> m_name;

c2_components/src/mfx_c2_decoder_component.cpp

@@ -21,6 +21,7 @@
 #include "mfx_c2_decoder_component.h"
 
 #include "mfx_debug.h"
+#include "mfx_intel_device.h"
 #include "mfx_msdk_debug.h"
 #include "mfx_c2_debug.h"
 #include "mfx_c2_components_registry.h"
@@ -178,6 +179,12 @@ MfxC2DecoderComponent::MfxC2DecoderComponent(const C2String name, const CreateCo
     MFX_DEBUG_TRACE_FUNC;
     const unsigned int SINGLE_STREAM_ID = 0u;
 
+    // We need to enable CPU access to the buffers of decoded images when
+    // 1. decode with DG2 and display with RPL-p iGPU;
+    // 2. decode with RPL-p iGPU and display with DG2.
+    // The displaying GPU will appear as virtio-GPU.
+    m_needCpuAccess = enforceLinearBuffer();
+
     addParameter(
         DefineParam(m_kind, C2_PARAMKEY_COMPONENT_KIND)
         .withConstValue(new C2ComponentKindSetting(C2Component::KIND_DECODER))
@@ -226,6 +233,11 @@ MfxC2DecoderComponent::MfxC2DecoderComponent(const C2String name, const CreateCo
         .build());
 
     m_consumerUsage = C2AndroidMemoryUsage::FromGrallocUsage(kDefaultConsumerUsage).expected;
+    // We need these flags in the case of hybrid GPU.
+    if (m_needCpuAccess) {
+        m_consumerUsage |= C2AndroidMemoryUsage::CPU_READ;
+        m_consumerUsage |= C2AndroidMemoryUsage::CPU_WRITE;
+    }
     addParameter(
         DefineParam(m_outputUsage, C2_PARAMKEY_OUTPUT_STREAM_USAGE)
         .withDefault(new C2StreamUsageTuning::output(SINGLE_STREAM_ID, m_consumerUsage))
@@ -1575,6 +1587,10 @@ void MfxC2DecoderComponent::DoUpdateMfxParam(const std::vector<C2Param*> &params
             case kParamIndexUsage: {
                 if (C2StreamUsageTuning::output::PARAM_TYPE == param->index()) {
                     m_consumerUsage = m_outputUsage->value;
+                    if (m_needCpuAccess) {
+                        m_consumerUsage |= C2AndroidMemoryUsage::CPU_READ;
+                        m_consumerUsage |= C2AndroidMemoryUsage::CPU_WRITE;
+                    }
                     // Set memory type according to consumer usage sent from framework
                     m_mfxVideoParams.IOPattern = (m_consumerUsage & (C2MemoryUsage::CPU_READ | C2MemoryUsage::CPU_WRITE)) ?
                         MFX_IOPATTERN_OUT_SYSTEM_MEMORY : MFX_IOPATTERN_OUT_VIDEO_MEMORY;

c2_utils/Android.bp

@@ -27,6 +27,7 @@ cc_library_static {
     ],
 
     shared_libs: [
+	"libdrm",
         "liblog",
         "libgralloctypes",
         "libstagefright_foundation",

c2_utils/include/mfx_c2_utils.h

@@ -130,7 +130,7 @@ void InitNV12PlaneLayout(uint32_t pitches[C2PlanarLayout::MAX_NUM_PLANES], C2Pla
 
 void InitNV12PlaneData(int32_t pitch_y, int32_t alloc_height, uint8_t* base, uint8_t** plane_data);
 
-int MfxFourCCToGralloc(mfxU32 fourcc, bool using_video_memory = true);
+int MfxFourCCToGralloc(mfxU32 fourcc, bool using_video_memory = false);
 
 bool IsYUV420(const C2GraphicView &view);
 

c2_utils/include/mfx_intel_device.h

@@ -0,0 +1,54 @@
+// Copyright (c) 2017-2021 Intel Corporation
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+
+#pragma once
+
+#include <stdint.h>
+
+enum {
+	GPU_GRP_TYPE_INTEL_IGPU_IDX = 0,
+	GPU_GRP_TYPE_INTEL_DGPU_IDX = 1,
+	GPU_GRP_TYPE_VIRTIO_GPU_BLOB_IDX = 2,
+	// virtio-GPU with allow-p2p feature, implying its display is backed by dGPU
+	GPU_GRP_TYPE_VIRTIO_GPU_BLOB_P2P_IDX = 3,
+	GPU_GRP_TYPE_VIRTIO_GPU_NO_BLOB_IDX = 4,
+	GPU_GRP_TYPE_VIRTIO_GPU_IVSHMEM_IDX = 5,
+	GPU_GRP_TYPE_NR,
+};
+
+#define GPU_GRP_TYPE_HAS_INTEL_IGPU_BIT			(1ull << GPU_GRP_TYPE_INTEL_IGPU_IDX)
+#define GPU_GRP_TYPE_HAS_INTEL_DGPU_BIT			(1ull << GPU_GRP_TYPE_INTEL_DGPU_IDX)
+#define GPU_GRP_TYPE_HAS_VIRTIO_GPU_BLOB_BIT		(1ull << GPU_GRP_TYPE_VIRTIO_GPU_BLOB_IDX)
+#define GPU_GRP_TYPE_HAS_VIRTIO_GPU_BLOB_P2P_BIT	(1ull << GPU_GRP_TYPE_VIRTIO_GPU_BLOB_P2P_IDX)
+#define GPU_GRP_TYPE_HAS_VIRTIO_GPU_NO_BLOB_BIT		(1ull << GPU_GRP_TYPE_VIRTIO_GPU_NO_BLOB_IDX)
+#define GPU_GRP_TYPE_HAS_VIRTIO_GPU_IVSHMEM_BIT		(1ull << GPU_GRP_TYPE_VIRTIO_GPU_IVSHMEM_IDX)
+
+#define DRIVER_DEVICE_FEATURE_I915_DGPU			(1ull << 1)
+#define DRIVER_DEVICE_FEATURE_VIRGL_RESOURCE_BLOB	(1ull << 2)
+#define DRIVER_DEVICE_FEATURE_VIRGL_QUERY_DEV		(1ull << 3)
+#define DRIVER_DEVICE_FEATURE_VIRGL_ALLOW_P2P		(1ull << 4)
+
+bool isIntelDg2(int fd);
+bool isVirtioGpuAllowP2p(int virtgpu_fd);
+bool isVirtioGpuPciDevice(int virtgpu_fd);
+bool isVirtioGpuWithBlob(int virtgpu_fd);
+
+uint64_t getGpuGroupType();
+bool enforceLinearBuffer();

c2_utils/src/mfx_c2_utils.cpp

@@ -22,6 +22,7 @@
 #include "mfx_c2_utils.h"
 #include "mfx_debug.h"
 #include "mfx_c2_debug.h"
+#include "mfx_intel_device.h"
 
 #include <iomanip>
 #include <sys/types.h>
@@ -573,6 +574,9 @@ int MfxFourCCToGralloc(mfxU32 fourcc, bool using_video_memory)
     MFX_DEBUG_TRACE_FUNC;
     MFX_DEBUG_TRACE_U32(fourcc);
 
+    if (enforceLinearBuffer()) {
+        using_video_memory = false;
+    }
     switch (fourcc)
     {
         case MFX_FOURCC_NV12:

c2_utils/src/mfx_intel_device.cpp

@@ -0,0 +1,332 @@
+#include <fcntl.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <log/log.h>
+#include <drm.h>
+#include <i915_drm.h>
+#include <virtgpu_drm.h>
+#include <xf86drm.h>
+
+#include "mfx_intel_device.h"
+
+#define ARRAY_SIZE(A) (sizeof(A) / sizeof(*(A)))
+
+#define GEN_VERSION_X10(dev)  ((dev)->graphics_version * 10 + (dev)->sub_version)
+
+#define VIRTGPU_PARAM_QUERY_DEV		11 /* Query the virtio device name. */
+#define VIRTGPU_PARAM_ALLOW_P2P		12
+
+struct intel_gpu_info {
+	int graphics_version;
+	int sub_version;
+	bool is_xelpd;
+};
+
+static int gem_param(int fd, int name)
+{
+	int v = -1; /* No param uses (yet) the sign bit, reserve it for errors */
+
+	struct drm_i915_getparam gp = {.param = name, .value = &v };
+	if (drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp))
+	      return -1;
+
+	  return v;
+}
+
+static int intel_gpu_info_from_device_id(uint16_t device_id, struct intel_gpu_info *i915)
+{
+	const uint16_t gen4_ids[] = { 0x29A2, 0x2992, 0x2982, 0x2972, 0x2A02, 0x2A12, 0x2A42,
+				      0x2E02, 0x2E12, 0x2E22, 0x2E32, 0x2E42, 0x2E92 };
+	const uint16_t gen5_ids[] = { 0x0042, 0x0046 };
+	const uint16_t gen6_ids[] = { 0x0102, 0x0112, 0x0122, 0x0106, 0x0116, 0x0126, 0x010A };
+	const uint16_t gen7_ids[] = {
+		0x0152, 0x0162, 0x0156, 0x0166, 0x015a, 0x016a, 0x0402, 0x0412, 0x0422,
+		0x0406, 0x0416, 0x0426, 0x040A, 0x041A, 0x042A, 0x040B, 0x041B, 0x042B,
+		0x040E, 0x041E, 0x042E, 0x0C02, 0x0C12, 0x0C22, 0x0C06, 0x0C16, 0x0C26,
+		0x0C0A, 0x0C1A, 0x0C2A, 0x0C0B, 0x0C1B, 0x0C2B, 0x0C0E, 0x0C1E, 0x0C2E,
+		0x0A02, 0x0A12, 0x0A22, 0x0A06, 0x0A16, 0x0A26, 0x0A0A, 0x0A1A, 0x0A2A,
+		0x0A0B, 0x0A1B, 0x0A2B, 0x0A0E, 0x0A1E, 0x0A2E, 0x0D02, 0x0D12, 0x0D22,
+		0x0D06, 0x0D16, 0x0D26, 0x0D0A, 0x0D1A, 0x0D2A, 0x0D0B, 0x0D1B, 0x0D2B,
+		0x0D0E, 0x0D1E, 0x0D2E, 0x0F31, 0x0F32, 0x0F33, 0x0157, 0x0155
+	};
+	const uint16_t gen8_ids[] = { 0x22B0, 0x22B1, 0x22B2, 0x22B3, 0x1602, 0x1606,
+				      0x160A, 0x160B, 0x160D, 0x160E, 0x1612, 0x1616,
+				      0x161A, 0x161B, 0x161D, 0x161E, 0x1622, 0x1626,
+				      0x162A, 0x162B, 0x162D, 0x162E };
+	const uint16_t gen9_ids[] = {
+		0x1902, 0x1906, 0x190A, 0x190B, 0x190E, 0x1912, 0x1913, 0x1915, 0x1916, 0x1917,
+		0x191A, 0x191B, 0x191D, 0x191E, 0x1921, 0x1923, 0x1926, 0x1927, 0x192A, 0x192B,
+		0x192D, 0x1932, 0x193A, 0x193B, 0x193D, 0x0A84, 0x1A84, 0x1A85, 0x5A84, 0x5A85,
+		0x3184, 0x3185, 0x5902, 0x5906, 0x590A, 0x5908, 0x590B, 0x590E, 0x5913, 0x5915,
+		0x5917, 0x5912, 0x5916, 0x591A, 0x591B, 0x591D, 0x591E, 0x5921, 0x5923, 0x5926,
+		0x5927, 0x593B, 0x591C, 0x87C0, 0x87CA, 0x3E90, 0x3E93, 0x3E99, 0x3E9C, 0x3E91,
+		0x3E92, 0x3E96, 0x3E98, 0x3E9A, 0x3E9B, 0x3E94, 0x3EA9, 0x3EA5, 0x3EA6, 0x3EA7,
+		0x3EA8, 0x3EA1, 0x3EA4, 0x3EA0, 0x3EA3, 0x3EA2, 0x9B21, 0x9BA0, 0x9BA2, 0x9BA4,
+		0x9BA5, 0x9BA8, 0x9BAA, 0x9BAB, 0x9BAC, 0x9B41, 0x9BC0, 0x9BC2, 0x9BC4, 0x9BC5,
+		0x9BC6, 0x9BC8, 0x9BCA, 0x9BCB, 0x9BCC, 0x9BE6, 0x9BF6
+	};
+	const uint16_t gen11_ids[] = { 0x8A50, 0x8A51, 0x8A52, 0x8A53, 0x8A54, 0x8A56, 0x8A57,
+				       0x8A58, 0x8A59, 0x8A5A, 0x8A5B, 0x8A5C, 0x8A5D, 0x8A71,
+				       0x4500, 0x4541, 0x4551, 0x4555, 0x4557, 0x4571, 0x4E51,
+				       0x4E55, 0x4E57, 0x4E61, 0x4E71 };
+	const uint16_t gen12_ids[] = {
+		0x4c8a, 0x4c8b, 0x4c8c, 0x4c90, 0x4c9a, 0x4680, 0x4681, 0x4682, 0x4683, 0x4688,
+		0x4689, 0x4690, 0x4691, 0x4692, 0x4693, 0x4698, 0x4699, 0x4626, 0x4628, 0x462a,
+		0x46a0, 0x46a1, 0x46a2, 0x46a3, 0x46a6, 0x46a8, 0x46aa, 0x46b0, 0x46b1, 0x46b2,
+		0x46b3, 0x46c0, 0x46c1, 0x46c2, 0x46c3, 0x9A40, 0x9A49, 0x9A59, 0x9A60, 0x9A68,
+		0x9A70, 0x9A78, 0x9AC0, 0x9AC9, 0x9AD9, 0x9AF8, 0x4905, 0x4906, 0x4907, 0x4908
+	};
+	const uint16_t adlp_ids[] = { 0x46A0, 0x46A1, 0x46A2, 0x46A3, 0x46A6, 0x46A8, 0x46AA,
+				      0x462A, 0x4626, 0x4628, 0x46B0, 0x46B1, 0x46B2, 0x46B3,
+				      0x46C0, 0x46C1, 0x46C2, 0x46C3, 0x46D0, 0x46D1, 0x46D2 };
+
+	const uint16_t dg2_ids[] = { // DG2 Val-Only Super-SKU: 4F80 - 4F87
+			0x4F80, 0x4F81, 0x4F82, 0x4F83, 0x4F84, 0x4F85, 0x4F86, 0x4F87,
+
+			// DG2 Desktop Reserved:  56A0 to 56AF
+			0x56A0, 0x56A1, 0x56A2, 0x56A3, 0x56A4, 0x56A5, 0x56A6, 0x56A7,
+			0x56A8, 0x56A9, 0x56AA, 0x56AB, 0x56AC, 0x56AD, 0x56AE, 0x56AF,
+
+			// DG2 Notebook Reserved:  5690 to 569F
+			0x5690, 0x5691, 0x5692, 0x5693, 0x5694, 0x5695, 0x5696, 0x5697,
+			0x5698, 0x5699, 0x569A, 0x569B, 0x569C, 0x569D, 0x569E, 0x569F,
+
+			// Workstation Reserved:  56B0 to 56BF
+			0x56B0, 0x56B1, 0x56B2, 0x56B3, 0x56B4, 0x56B5, 0x56B6, 0x56B7,
+			0x56B8, 0x56B9, 0x56BA, 0x56BB, 0x56BC, 0x56BD, 0x56BE, 0x56BF,
+
+			// Server Reserved:  56C0 to 56CF
+			0x56C0, 0x56C1, 0x56C2, 0x56C3, 0x56C4, 0x56C5, 0x56C6, 0x56C7,
+			0x56C8, 0x56C9, 0x56CA, 0x56CB, 0x56CC, 0x56CD, 0x56CE, 0x56CF
+	};
+
+	const uint16_t rplp_ids[] = { 0xA720, 0xA721, 0xA7A0, 0xA7A1, 0xA7A8, 0xA7A9 };
+
+	const uint16_t mtl_ids[] = { 0x7D40, 0x7D60, 0x7D45, 0x7D55, 0x7DD5 };
+
+	unsigned i;
+	/* Gen 4 */
+	for (i = 0; i < ARRAY_SIZE(gen4_ids); i++)
+		if (gen4_ids[i] == device_id) {
+			i915->graphics_version = 4;
+			i915->sub_version = 0;
+			i915->is_xelpd = false;
+			return 0;
+		}
+
+	/* Gen 5 */
+	for (i = 0; i < ARRAY_SIZE(gen5_ids); i++)
+		if (gen5_ids[i] == device_id) {
+			i915->graphics_version = 5;
+			i915->sub_version = 0;
+			i915->is_xelpd = false;
+			return 0;
+		}
+
+	/* Gen 6 */
+	for (i = 0; i < ARRAY_SIZE(gen6_ids); i++)
+		if (gen6_ids[i] == device_id) {
+			i915->graphics_version = 6;
+			i915->sub_version = 0;
+			i915->is_xelpd = false;
+			return 0;
+		}
+
+	/* Gen 7 */
+	for (i = 0; i < ARRAY_SIZE(gen7_ids); i++)
+		if (gen7_ids[i] == device_id) {
+			i915->graphics_version = 7;
+			return 0;
+		}
+
+	/* Gen 8 */
+	for (i = 0; i < ARRAY_SIZE(gen8_ids); i++)
+		if (gen8_ids[i] == device_id) {
+			i915->graphics_version = 8;
+			i915->sub_version = 0;
+			i915->is_xelpd = false;
+			return 0;
+		}
+
+	/* Gen 9 */
+	for (i = 0; i < ARRAY_SIZE(gen9_ids); i++)
+		if (gen9_ids[i] == device_id) {
+			i915->graphics_version = 9;
+			i915->sub_version = 0;
+			i915->is_xelpd = false;
+			return 0;
+		}
+
+	/* Gen 11 */
+	for (i = 0; i < ARRAY_SIZE(gen11_ids); i++)
+		if (gen11_ids[i] == device_id) {
+			i915->graphics_version = 11;
+			i915->sub_version = 0;
+			i915->is_xelpd = false;
+			return 0;
+		}
+
+	/* Gen 12 */
+	for (i = 0; i < ARRAY_SIZE(gen12_ids); i++)
+		if (gen12_ids[i] == device_id) {
+			i915->graphics_version = 12;
+			i915->sub_version = 0;
+			i915->is_xelpd = false;
+			return 0;
+		}
+
+	for (i = 0; i < ARRAY_SIZE(dg2_ids); i++)
+		if (dg2_ids[i] == device_id) {
+			i915->graphics_version = 12;
+			i915->sub_version = 5;
+			i915->is_xelpd = false;
+			return 0;
+		}
+
+	for (i = 0; i < ARRAY_SIZE(adlp_ids); i++)
+		if (adlp_ids[i] == device_id) {
+			i915->graphics_version = 12;
+			i915->sub_version = 5;
+			i915->is_xelpd = true;
+			return 0;
+		}
+
+	for (i = 0; i < ARRAY_SIZE(rplp_ids); i++)
+		if (rplp_ids[i] == device_id) {
+			i915->graphics_version = 12;
+			i915->sub_version = 0;
+			i915->is_xelpd = true;
+			return 0;
+		}
+
+	for (i = 0; i < ARRAY_SIZE(mtl_ids); i++)
+		if (mtl_ids[i] == device_id) {
+			i915->graphics_version = 14;
+			i915->sub_version = 0;
+			i915->is_xelpd = false;
+			return 0;
+		}
+
+	return -1;
+}
+
+bool isIntelDg2(int fd)
+{
+	int ret;
+	uint16_t device_id;
+	struct intel_gpu_info info;
+
+	ret = gem_param(fd, I915_PARAM_CHIPSET_ID);
+	if (ret == -1) {
+		return false;
+	}
+	device_id = (uint16_t) ret;
+	ret = intel_gpu_info_from_device_id(device_id, &info);
+	return GEN_VERSION_X10(&info) == 125;
+}
+
+bool isVirtioGpuAllowP2p(int virtgpu_fd) {
+	struct drm_virtgpu_getparam get_param = { 0, 0 };
+	uint64_t value = 0;
+	get_param.param = VIRTGPU_PARAM_ALLOW_P2P;
+	get_param.value = (__u64) &value;
+	int ret = drmIoctl(virtgpu_fd, DRM_IOCTL_VIRTGPU_GETPARAM, &get_param);
+	if (ret || value != 1) {
+		return false;
+	}
+	return true;
+}
+
+bool isVirtioGpuPciDevice(int virtgpu_fd) {
+	struct drm_virtgpu_getparam get_param = { 0, 0 };
+	uint64_t value = 0;
+	get_param.param = VIRTGPU_PARAM_QUERY_DEV;
+	get_param.value = (__u64) &value;
+	int ret = drmIoctl(virtgpu_fd, DRM_IOCTL_VIRTGPU_GETPARAM, &get_param);
+	if (ret || value != 1) {
+		return false;
+	}
+	return true;
+}
+
+bool isVirtioGpuWithBlob(int virtgpu_fd) {
+	struct drm_virtgpu_getparam get_param = { 0, 0 };
+	uint64_t value = 0;
+	get_param.param = VIRTGPU_PARAM_RESOURCE_BLOB;
+	get_param.value = (__u64) &value;
+	int ret = drmIoctl(virtgpu_fd, DRM_IOCTL_VIRTGPU_GETPARAM, &get_param);
+	if (ret || value != 1) {
+		return false;
+	}
+	return true;
+}
+
+uint64_t getGpuGroupType() {
+    static bool cached = false;
+    static uint64_t gpu_grp_type = 0;
+    if (cached) {
+        return gpu_grp_type;
+    }
+    for (int i = 0; i < 16; ++i) {
+        char path[64];
+        snprintf(path, sizeof(path), "/dev/dri/renderD%d", 128 + i);
+        int fd = open(path, O_RDWR | O_CLOEXEC);
+        if (fd < 0) {
+            continue;
+        }
+        drmVersionPtr version = drmGetVersion(fd);
+        if (version == NULL) {
+            close(fd);
+            continue;
+        }
+        if (strcmp(version->name, "i915") == 0) {
+            if (isIntelDg2(fd)) {
+                gpu_grp_type |= GPU_GRP_TYPE_HAS_INTEL_DGPU_BIT;
+            } else {
+                gpu_grp_type |= GPU_GRP_TYPE_HAS_INTEL_IGPU_BIT;
+            }
+        } else if (strcmp(version->name, "virtio_gpu") == 0) {
+            if (!isVirtioGpuPciDevice(fd)) {
+                gpu_grp_type |= GPU_GRP_TYPE_HAS_VIRTIO_GPU_IVSHMEM_BIT;
+            } else {
+                if (!isVirtioGpuWithBlob(fd)) {
+                    gpu_grp_type |= GPU_GRP_TYPE_HAS_VIRTIO_GPU_NO_BLOB_BIT;
+                } else {
+                    if (isVirtioGpuAllowP2p(fd)) {
+                        gpu_grp_type |= GPU_GRP_TYPE_HAS_VIRTIO_GPU_BLOB_P2P_BIT;
+                    } else {
+                        gpu_grp_type |= GPU_GRP_TYPE_HAS_VIRTIO_GPU_BLOB_BIT;
+                    }
+                }
+            }
+        }
+        drmFreeVersion(version);
+        close(fd);
+    }
+    cached = true;
+    return gpu_grp_type;
+}
+
+bool enforceLinearBuffer() {
+    // virtio-GPU without blob feature cannot import external buffers at all,
+    // we must use linear system memory buffers.
+    uint64_t gpu_grp_type = getGpuGroupType();
+    if (gpu_grp_type & GPU_GRP_TYPE_HAS_VIRTIO_GPU_NO_BLOB_BIT) {
+        return true;
+    }
+    // virtio-GPU backed by DG2 (virtio-GPU with ALLOW_P2P feature) whereas
+    // rendering/decoding uses iGPU.
+    if ((gpu_grp_type & GPU_GRP_TYPE_HAS_VIRTIO_GPU_BLOB_P2P_BIT) &&
+        (gpu_grp_type & GPU_GRP_TYPE_HAS_INTEL_IGPU_BIT)) {
+        return true;
+    }
+    // virtio-GPU backed by iGPU whereas rendering/decoding uses DG2.
+    if ((gpu_grp_type & GPU_GRP_TYPE_HAS_VIRTIO_GPU_BLOB_BIT) &&
+        (gpu_grp_type & GPU_GRP_TYPE_HAS_INTEL_DGPU_BIT)) {
+        return true;
+    }
+    return false;
+}
+