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Add 'wait for' clause to output-only VHDL models #512

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merged 1 commit into from
Jan 31, 2024
Merged

Add 'wait for' clause to output-only VHDL models #512

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1 change: 1 addition & 0 deletions qucs/components/logic_0.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -78,6 +78,7 @@ QString logic_0::vhdlCode( int )
s = "\n " + Name + ":process\n" +
" begin\n " +
LO + " <= '0';\n" +
" wait for 1 ns;\n" +
" end process;\n";
return s;
}
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1 change: 1 addition & 0 deletions qucs/components/logic_1.cpp
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Expand Up @@ -79,6 +79,7 @@ QString logic_1::vhdlCode( int )
s = "\n " + Name + ":process\n" +
" begin\n " +
L1 + " <= '1';\n" +
" wait for 1 ns;\n" +
" end process;\n";
return s;
}
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3 changes: 2 additions & 1 deletion qucs/components/pad2bit.cpp
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Expand Up @@ -81,7 +81,8 @@ QString pad2bit::vhdlCode( int )
" when 3 => "+A+" <= '1'; "+B+" <= '1';\n" +
" when others => null;\n" +
" end case;\n";
s3 = " end process;\n";
s3 = " wait for 1 ns;\n"
" end process;\n";
s = s1+s2+s3;
return s;
}
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3 changes: 2 additions & 1 deletion qucs/components/pad3bit.cpp
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Expand Up @@ -89,7 +89,8 @@ QString pad3bit::vhdlCode( int )
" when 7 => "+A+" <= '1'; "+B+" <= '1'; "+C+" <= '1';\n"+
" when others => null;\n" +
" end case;\n";
s3 = " end process;\n";
s3 = " wait for 1 ns;\n"
" end process;\n";
s = s1+s2+s3;
return s;
}
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3 changes: 2 additions & 1 deletion qucs/components/pad4bit.cpp
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Expand Up @@ -102,7 +102,8 @@ QString pad4bit::vhdlCode( int )
" when 15 => "+A+" <= '1'; "+B+" <= '1'; "+C+" <= '1'; "+D+" <= '1';\n"+
" when others => null;\n"
" end case;\n";
s3 = " end process;\n";
s3 = " wait for 1 ns;\n"
" end process;\n";
s = s1+s2+s3;
return s;
}
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