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Add test for tmp variable outside when/otherwise blocks
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rameloni committed Jul 11, 2024
1 parent 3ed630f commit a8f30e8
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Showing 2 changed files with 11 additions and 1 deletion.
Original file line number Diff line number Diff line change
Expand Up @@ -297,6 +297,7 @@ object TywavesAnnotationCircuits {
val out = IO(Output(UInt(8.W)))
val sel = IO(Input(UInt(math.sqrt(8).ceil.toInt.W)))

val tmp = sel + 1.U
when(sel % 2.U === 0.U) {
val outTmp = inSeq(sel)
val evenSel = outTmp + 1.U
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Original file line number Diff line number Diff line change
Expand Up @@ -206,8 +206,17 @@ class TypeAnnotationDataTypesSpec extends AnyFunSpec with Matchers with chiselTe
(createExpected("~TopCircuitWhenElse\\|TopCircuitWhenElse>sel", "UInt<3>", "IO"), 1),
// Tmp
(createExpected("~TopCircuitWhenElse\\|TopCircuitWhenElse>evenSel", "UInt<8>", "OpResult"), 1),
(createExpected("~TopCircuitWhenElse\\|TopCircuitWhenElse>_evenSel_T", "UInt<9>", "OpResult"), 1),
(createExpected("~TopCircuitWhenElse\\|TopCircuitWhenElse>oddSel", "UInt<8>", "OpResult"), 1),
(createExpected("~TopCircuitWhenElse\\|TopCircuitWhenElse>selIsOne", "UInt<8>", "OpResult"), 1)
(createExpected("~TopCircuitWhenElse\\|TopCircuitWhenElse>_oddSel_T", "UInt<9>", "OpResult"), 1),
(createExpected("~TopCircuitWhenElse\\|TopCircuitWhenElse>selIsOne", "UInt<8>", "OpResult"), 1),
(createExpected("~TopCircuitWhenElse\\|TopCircuitWhenElse>_selIsOne_T", "UInt<9>", "OpResult"), 1),
(createExpected("~TopCircuitWhenElse\\|TopCircuitWhenElse>tmp", "UInt<3>", "OpResult"), 1),
(createExpected("~TopCircuitWhenElse\\|TopCircuitWhenElse>_tmp_T", "UInt<4>", "OpResult"), 1),
(createExpected("~TopCircuitWhenElse\\|TopCircuitWhenElse>_T", "UInt<2>", "OpResult"), 1),
(createExpected("~TopCircuitWhenElse\\|TopCircuitWhenElse>_T_1", "Bool", "OpResult"), 1),
(createExpected("~TopCircuitWhenElse\\|TopCircuitWhenElse>_T_2", "Bool", "OpResult"), 1),

)
checkAnno(expectedMatches, string)
// format: on
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